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AM85C30 Datasheet(PDF) 24 Page - Advanced Micro Devices |
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AM85C30 Datasheet(HTML) 24 Page - Advanced Micro Devices |
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24 / 68 page  AMD 24 Am85C30 Interrupt Acknowledge Cycle Timing NO TAG illustrates Interrupt Acknowledge cycle timing. Between the time INTACK goes Low and the falling edge of RD, the internal and external IEI/IEO daisy chains settle. If there is an interrupt pending in the ESCC and IEI is High when RD falls, the Acknowledge cycle is intended for the SCC. In this case, the ESCC may be programmed to respond to RD Low by placing its inter- rupt vector on D7–D0 ; it then sets the appropriate Inter- rupt-Under-Service latch internally. Address Valid Data Valid A/ B, D/C INTACK CE WR D7 –D0 Figure 10. Read Cycle Timing 10216F-14 Address Valid Data Valid A/ B, D/C INTACK CE WR D7 –D0 Figure 11. Write Cycle Timing 10216F-15 Vector INTACK RD D7 –D0 Figure 12. Interrupt Acknowledge Cycle Timing 10216F-16 |
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