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AM85C30 Datasheet(PDF) 66 Page - Advanced Micro Devices |
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AM85C30 Datasheet(HTML) 66 Page - Advanced Micro Devices |
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66 / 68 page ![]() A M E N D M E N T AMD 13 Am85C30 SWITCHING CHARACTERISTICS over MILITARY/INDUSTRIAL operating range (continued) Read and Write Timing (see Figure 21) 1 TwPCI PCLK Low Width 50 1000 40 1000 26 1000 22 1000 ns 2 TwPCh PCLK High Width 50 1000 40 1000 26 1000 22 1000 ns 3 TfPC PCLK Fall Time 15 12 8 5 ns 4 TrPC PCLK Rise Time 15 12 8 5 ns 5 TcPC PCLK Cycle Time 122 2000 100 2000 61 2000 50 2000 ns 6 TsA(WR) Address to WR ↓ Setup Time 70 50 35 30 ns 7 ThA(WR) Address to WR ↑ Hold Time 0000 ns 8 TsA(RD) Address to RD ↓ Setup Time 70 50 35 30 ns 9 ThA(RD) Address to RD ↑ Hold Time 0000 ns 10 TsIA(PC) I NTACK to PCLK ↑ Setup Time 20 20 15 15 ns 11 TsIA(WR) INTACK to WR ↓ Setup Time 145 120 70 65 ns (Note 1) 12 ThIA(WR) INTACK to WR ↑ Hold Time 0000 ns 13 TsIA(RD) INTACK to RD ↓ Setup Time 145 120 70 65 ns (Note 1) 14 ThIAi(RD) INTACK to RD ↑ Hold Time 0000 ns 15 ThIA(PC) INTACK to PCLK ↑ Hold Time 40 30 15 15 ns 16 TsCEI(WR) CE Low to WR ↓ Setup Time 0000 ns 17 ThCE(WR) CE to WR ↑ Hold Time 0000 ns 18 TsCEh(WR) CE High to WR ↓ Setup Time 60 50 30 25 ns 19 TsCEI(RD) CE Low to RD ↓ Setup Time 0000 ns (Note 1) 20 ThCE(RD) CE to RD ↑ Hold Time (Note1) 0000 ns 21 TsCEh(RD) CE High to RD ↓ Setup Time 60 50 30 25 ns (Note 1) 22 TwRDI RD Low Width (Note 1) 150 125 75 65 ns 23 TdRD(DRA) RD ↓ to Read Data Active Delay 0000 ns 24 TdRDr(DR) RD ↑ to Read Data Not Valid Delay 0000 ns 25 TdRDf(DR) RD ↓ to Read Data Valid Delay 140 125 70 65 ns 26 TdRD(DRz) RD ↑ to Read Data Float Delay 40 35 20 20 ns (Note 2) Notes: 1. Parameter does not apply to Interrupt Acknowledge transactions. 2. Float delay is defined as the time at which the data bus is released from its drive state with a maximum DC load and minimum AC load. No. Parameter Symbol Parameter Description 10 MHz 20 MHz Min Max Min Max Unit 8.192 MHz Min Max Min Max 16.384 MHz Industrial Only |
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