ASI4U datasheet(16/71 Pages) RENESAS

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ASI4U / ASI4U-E / ASI4U-F Datasheet

January 26, 2016

3.3.4.

Data Port Pins

An important feature of the ASI4U/ASI4U-E/ASI4U-F is the 8-bit wide data port that consists of a 4-bit-wide input

section and a 4-bit-wide output section. The input and output sections work independently from each other

allowing a maximum of 8 devices (4 input and 4 output devices) to be connected to the ASI4U/ASI4U-E/ASI4U-F.

For special applications (compatibility), the Multiplex Mode can be activated, which limits the output activation to a

specific time frame. With this feature, a 4-bit wide bi-directional data I/O port can be achieved by external

connection of the corresponding data input and output pins.

The data port is accompanied by the data strobe signal on the DSR pin. There is a defined phase relation

between a data output event, the input data sampling, and the activation of the DSR signal, so it can be used to

trigger external logic or a microcontroller to process the received data or to provide new input data for the AS-i

slave response. See section 4.7 for further details.

3.3.5.

Data Input Inversion

By default, the logic signal (HIGH/LOW) that is present at the data input pins during the input sampling phase is

transferred without modification to the send register, which is interfaced by the UART so that the signal directly

becomes part of the slave response.

Some applications function with inverted logic levels. To avoid additional external inverters, the input signal can

be inverted by the ASI4U/ASI4U-E/ASI4U-F before the signal is transferred to the send register. The inversion of

the input signals can either be done bit-selectively or jointly for all data input pins. See section 4.7.2.

3.3.6.

Data Input Filtering

To prevent input signal bouncing being transferred to the AS-Interface Master, the data input signals can be

digitally filtered. Filter times can be configured in seven steps from 128µs up to 8.192ms. When the AS-i Cycle

Mode is activated, the filter time is determined by the actual AS-i cycle time. For more detailed information, refer

to section 4.7.2.

The filter function can be enabled bit-selectively. Activation of the filters can be done jointly either by EEPROM

configuration or by the logic state of the parameter port pin P2. See section 4.7.2.

3.3.7.

Fixed-Data Output Driving

The fixed-data output-driving feature is intended to facilitate board-level design for similar products that do not

require the full data output port width. The user can select one or more bits from the data output port to be driven

by a distinct logic level instead of by the data that was sent by the master. The distinct output data is stored in the

EEPROM and can be set during final module configuration. With this feature, it is possible to signal the actual IC

profile to external circuitry and to allow reuse of some types of board designs for different product applications.

See section 4.7.3.

ASI4U Datasheet(PDF) 16 Page - Renesas Technology Corp