DA7212 datasheet(40/136 Pages) RENESAS

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DA7212

Ultra-Low Power Stereo Codec

Datasheet

Revision 3.5

05-Jan-2022

CFR0011-120-00

40 of 135

Table 28: CP_THRESH_VDD2 settings in signal size mode (CP_MCHANGE = 11)

CP_THRESH_VDD2 setting

Approximate switching

point (Note 14)

Notes

0x00

Never

Not recommended. Always VDD/1 mode

0x01

Never

Not recommended. Always VDD/1 mode

0x02

-32 dBFS

Not recommended. Very power-inefficient as

nearly always VDD/1

0x03

-24 dBFS

Good to use

0x04

-20 dBFS

Good to use

0x05

-17 dBFS

Good to use

0x06

-15 dBFS

Recommended setting

0x07

-13 dBFS

Good to use

0x08

-12 dBFS

Good to use

0x09

-11 dBFS

Good to use

0x0A

-10 dBFS

Good to use

0x0B

-9 dBFS

Not recommended. VDD/2 begins to clip

0x0C

Never

Not recommended. Always VDD/2 mode

0x0D

Never

Not recommended. Always VDD/2 mode

0x0E

Never

Not recommended. Always VDD/2 mode

0x0F

Never

Not recommended. Always VDD/2 mode

Note 14 Full Scale (FS) = 1.6 * VDD_A

13.16 Charge Pump Clock Control

The charge pump on DA7212 requires two clocks (cp_clk and cp_clk2). The cp_clk2 clock runs at a

slower frequency than cp_clk. It is cp_clk that actually clocks the charge pump.

To prevent the clocks stopping in an unknown state, there are always two pulses on cp_clk for every

one pulse of cp_clk2. This is illustrated in Figure 12.

cp_clk

clk

cp_clk2

Figure 12: Input (clk) and output clocks (cp_clk and cp_clk2) at CP_FCONTROL = 010

When CP_ANALOGUE_LVL = 00 (‘No feedback’ – see Section 13.17 for more details), the charge

pump’s nominal clock rate cp_clk is controlled by CP_FCONTROL, providing a range from 1 MHz

(CP_FCONTROL = 000) down to 63 kHz (CP_FCONTROL = 100). With the slower clock rates,

quiescent power consumption is lower but the trade-off is a reduced load current, and slower

changes to the voltage.

Section 13.17 describes how quiescent power and load current can be varied according to demand.

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