DA7212 datasheet(49/136 Pages) RENESAS

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DA7212

Ultra-Low Power Stereo Codec

Datasheet

Revision 3.5

05-Jan-2022

CFR0011-120-00

49 of 135

Figure 19: Equaliser filter band 5 frequency response at FS = 48 kHz

13.23 Soft Mute

To improve the user’s perception of audio reconfigurations, the DAC channel signals may be soft

muted by asserting the control DAC_SOFTMUTE_EN. The soft mute function attenuates the digital

input to the DAC, ramping the gain down in steps of 0.1875 dB from its current level to -77.25 dB,

then completely muting the channel. When DAC_SOFTMUTE_EN is released, the attenuation is set

to 77.25 dB, and then ramped up to the previous gain level. Both left and right channels of Soft Mute

enabled output amplifiers are muted simultaneously. The ramping up and down rate is dependent on

the audio sample rate and can be individually configured using control DAC_SOFTMUTE_RATE.

During active soft muting, the digital gain of the DAC will be different to the value programmed inside

controls DAC_L_DIGITAL_GAIN_STATUS and DAC_R_DIGITAL_GAIN_STATUS.

13.24 Playback Noise-Gate

Noise-gate is an automatic gain control for DAC playback that reduces the noise heard during

playback if no signal is present. It is enabled using the DAC_NG_EN control.

When the output signals on both channels are below a given threshold level, and they stay low for

longer than a specified period, then playback noise-gate is activated. When the playback noise-gate

activates, the gain on the active HP and Line amplifiers are ramped down to their lowest levels. This

is equivalent to asserting the minimum-gain controls HP_L_AMP_MIN_GAIN_EN,

HP_R_AMP_MIN_GAIN_EN and LINE_AMP_MIN_GAIN_EN.

The Noise-Gate Threshold Level can be specified in 6 dB steps from 90 dB to 48 dB. The Noise-

Gate Threshold Time ranges from 256 samples to 2048 samples and is set using the control

DAC_NG_SETUP_TIME.

When the averaged level of the two channels exceeds the release threshold configured in

DAC_NG_OFF_THRESHOLD, the gain of the amplifiers is ramped up back to its original value.

When the average level of the two channels is below the attack threshold configured in

DAC_NG_ON_THRESHOLD for longer than the time specified in DAC_NG_SETUP_TIME, the gain

is ramped down to its minimum value.

The attack and release rate can be configured via controls DAC_NG_RAMPDN_RATE and

DAC_NG_RAMPUP_RATE. The Noise-gate release time is usually much faster than the attack time,

to allow a proper playback as soon as a signal is present at the output amplifiers.

13.25 Clock Modes

The DA7212 requires a clock for operation of various circuits within the chip. There are four ways in

which the main system clock may be generated:

● PLL bypass mode: If digital playback or record is required, the MCLK frequency should be set to

one of 11.2896/12.288 MHz or 22.5792/24.576 MHz or 45.1584/49.152 MHz (Note 17). The

PLL_INDIV register bit must then be programmed accordingly

● Normal PLL mode: Alternative frequency clock applied to MCLK pin (in the range of 2 to 50

MHz), where MCLK is synchronous with WCLK, or Master Mode is enabled

● SRM PLL mode: Clock applied to MCLK pin (in the range of 2 to 50 MHz) is asynchronous to

WCLK

● 32 kHz mode: Watch crystal frequency (32.768 kHz) clock applied to MCLK

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