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DA7212 Datasheet(PDF) 61 Page - Renesas Technology Corp |
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DA7212 Datasheet(HTML) 61 Page - Renesas Technology Corp |
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61 / 136 page  DA7212 Ultra-Low Power Stereo Codec Datasheet Revision 3.5 05-Jan-2022 CFR0011-120-00 61 of 135 © 2022 Renesas Electronics 13.37 DSP Mode In DSP mode (DAI_FORMAT = 3), the rising edge of the word clock starts the data transfer with the left channel data first and immediately followed by the right channel data. Each data bit is valid on the falling edge of the bit clock. BCLK WCLK msb Left Channel lsb msb Right Channel lsb DATIN/DATOUT msb The falling edge of WCLK can occur anywhere in this area The falling edge of WCLK can occur anywhere in this area BCLK WCLK msb Left Channel lsb msb Right Channel lsb DATIN/DATOUT msb Offset Figure 32: DSP mode |
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