DA9213 datasheet(28/63 Pages) RENESAS

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DA9213, DA9214, and DA9215

Multi-Phase 5A/Phase DC-DC Buck Converter

Datasheet

Revision 3.4

10-Feb-2022

CFR0011-120-00

28 of 62

7.2

Ports Description

This section describes the functionality of each input / output port.

7.2.1

VDDIO

VDDIO is an independent IO supply rail input to DA9213, DA9214, and DA9215 that can be assigned

to the power manager interface and to the GPIOs (see control PM_IF_V and GPI_V). The rail

assignment determines the IO voltage levels and logical thresholds (see also the Digital I/O

Characteristics in Table 7).

An integrated under-voltage lockout circuit for the VDDIO prevents internal errors by disabling the I2C

communication when the voltage drops below VULO_IO. In that case the buck converters are also

disabled and cannot be re-enabled (even via input port) until the VDDIO under-voltage condition has

been resolved. At the exit of the VDDIO under-voltage condition an event E_UVLO_IO is generated

and the nIRQ line is driven active if the event is not masked.

The VDDIO under-voltage circuit monitors voltages relative to a nominal voltage of 1.8V. If a different

rail voltage is being used, the under-voltage circuit can be disabled via UVLO_IO_DIS.

Note that the maximum speed at 4-WIRE interface is only available if the selected supply rail is

greater than 1.6 V.

7.2.2

IC_EN

IC_EN is a general enable signal for DA9213, DA9214, and DA9215, turning on and off the internal

circuitry (for example, the reference, the digital core, etc.). Correct control of this port has a direct

impact on the quiescent current of the whole application. A low level of IC_EN allows the device to

reach the minimum quiescent current. The voltage at this pin is continuously sensed by a dedicated

analog circuit.

The host processor will be allowed to start the communication with DA9213, DA9214, and DA9215

through the Control Interface and, for example to turn on the buck converters, a delay time of tEN after

assertion of the IC_EN pin. If the bucks are enabled via OTP (see BUCKA_EN and BUCKB_EN

controls), they will start up automatically after assertion of IC_EN.

The IC_EN activation threshold is defined with a built-in hysteresis to avoid glitching transitions that

take place with unstable rising or falling edges.

7.2.3

nIRQ

The nIRQ port indicates that an interrupt causing event has occurred and that the event/status

information is available in the related registers. The nIRQ is an output signal that can either be push

pull or open drain (selected via IRQ_TYPE). If an active high IRQ signal is required, it can be

achieved by asserting control IRQ_LEVEL (recommended for push-pull mode).

Examples of this type of information can be critical temperature and voltage, fault conditions, status

changes at GPI ports, and so forth. The event registers hold information about the events that have

occurred. Events are triggered by a status change at the monitored signals. When an event bit is set,

the nIRQ signal is asserted unless this interrupt is masked by a bit in the IRQ mask register. The

nIRQ will not be released until all event registers with asserted bits have been read and cleared. New

events that occur during reading an event register are held until the event register has been cleared,

ensuring that the host processor does not miss them.

DA9213 Datasheet(PDF) 28 Page - Renesas Technology Corp

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