EM783 datasheet(2/58 Pages) NXP

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EM783

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Product data sheet

Rev. 2 — 17 January 2014

2 of 58

NXP Semiconductors

EM783

Energy metering IC; 32 kB flash, 8 kB SRAM, 4 kB EEPROM

 Digital peripherals:

 Up to 22 General Purpose I/O (GPIO) pins with configurable pull-up/pull-down

resistors, repeater mode, and open-drain mode.

 Up to 9 pins are configurable with a digital input glitch filter for removing glitches

with widths of 10 ns. Two pins are configurable for 20ns glitch filter and another

two pins are configurable for 50 ns glitch filters.

 GPIO pins can be used as edge and level sensitive interrupt sources.

 High-current source output driver (20 mA) on one pin (P0_21).

 High-current sink driver (20 mA) on true open-drain pins (P0_2 and P0_3).

 Two general-purpose counter/timers with a total of up to four capture inputs and

five match outputs.

 Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal

low-power WatchDog Oscillator (WDOsc).

 Analog peripherals:

 Metrology engine for smart metering with one voltage input, one bias input, from

two up to six current inputs and a temperature sensor.

 Internal voltage reference.

 10-bit DAC with flexible conversion triggering.

 Serial interfaces:

 USART with fractional baud rate generation, internal FIFO, support for

RS-485/9-bit mode and synchronous mode.

 One SSP controller with FIFO and multi-protocol capabilities.

 I2C-bus interface supporting the full I2C-bus specification and Fast-mode Plus with

a data rate of 1 Mbit/s with multiple address recognition and monitor mode.

 Clock generation:

 Crystal Oscillator (SysOsc) with an operating range of 1 MHz to 25 MHz.

 12 MHz internal RC Oscillator (IRC) trimmed to 1 % accuracy that can optionally be

used as a system clock.

 Internal low-power, Low-Frequency Oscillator (LFOsc) with programmable

frequency output.

 Clock input for external system clock (25 MHz typical).

 PLL allows CPU operation up to the maximum CPU rate with the IRC, the external

clock, or the SysOsc as clock sources.

 Clock output function with divider that can reflect the SysOsc, the IRC, the main

clock, or the LFOsc.

 Power control:

 Supports ARM Cortex-M0 Sleep mode as reduced power mode.

 Power profiles residing in boot ROM allowed to optimize performance and

minimize power consumption for any given application through one simple function

call.

 Processor wake-up from reduced power mode using any interrupt.

 Power-On Reset (POR).

 BrownOut Detect (BOD) with two separate programmable thresholds for interrupt

and one hardware controlled reset trip point.

 POR and BOD are always enabled for rapid UVLO protection against power supply

voltage drops below 2.4 V.

 Unique device serial number for identification.

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