EM783-SC datasheet(41/58 Pages) NXP

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EM783

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Product data sheet

Rev. 2 — 17 January 2014

41 of 58

NXP Semiconductors

EM783

Energy metering IC; 32 kB flash, 8 kB SRAM, 4 kB EEPROM

[1]

See the I2C-bus specification UM10204 for details.

[2]

Parameters are valid over operating temperature range unless otherwise specified.

[3]

tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission

and the acknowledge.

[4]

A device must provide an internal hold time of at least 300 ns for the SDA signal (with respect to the

VIH(min) of the SCL signal). The hold time is to bridge the undefined region of the falling edge of SCL.

[5]

Cb = total capacitance of one bus line in pF.

[6]

The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA

output stage tf is specified at 250 ns. This allows series protection resistors to be connected in between the

SDA and the SCL pins and the SDA/SCL bus lines without exceeding the maximum specified tf.

[7]

In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors

are used, designers should allow for this when considering bus timing.

[8]

The maximum tHD;DAT can be 3.45 s and 0.9 s for Standard-mode and Fast-mode but must be less than

the maximum of tVD;DAT or tVD;ACK by a transition time (see UM10204). This maximum must only be met if

the device does not stretch the LOW period (tLOW) of the SCL signal. If the clock stretches the SCL, the

data must be valid by the set-up time before it releases the clock.

[9]

tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL. It applies to data in

transmission and the acknowledge.

[10] A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system but the requirement tSU;DAT =

250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the

SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit

to the SDA line tr(max) + tSU;DAT = 1000 + 250 = 1250 ns before the SCL line is released. This is in

accordance with the Standard-mode I2C-bus specification. Also the acknowledge timing must meet this

set-up time.

tHIGH

HIGH period of

the SCL clock

Standard-mode

4.0

s

Fast-mode

0.6

s

Fast-mode Plus

0.26

s

tHD;DAT

data hold time

[3][4][8]

Standard-mode

s

Fast-mode

s

Fast-mode Plus

s

tSU;DAT

data set-up

time

[9][10]

Standard-mode

250

Fast-mode

100

Fast-mode Plus

Table 16.

Dynamic characteristic: I2C-bus pins[1] …continued

Tamb = 40 C to +85 C.[2]

Symbol

Parameter

Conditions

Min

Max

Unit

Fig 18. I2C-bus pins clock timing

002aaf425

70 %

30 %

SDA

70 %

30 %

70 %

30 %

70 %

30 %

tHD;DAT

SCL

1 / fSCL

70 %

30 %

70 %

30 %

tVD;DAT

tHIGH

tLOW

tSU;DAT

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