EM783-SC datasheet(56/58 Pages) NXP

56 / 58 page

EM783

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Product data sheet

Rev. 2 — 17 January 2014

56 of 58

NXP Semiconductors

EM783

Energy metering IC; 32 kB flash, 8 kB SRAM, 4 kB EEPROM

19. Tables

Table 1.

Ordering information . . . . . . . . . . . . . . . . . . . . .3

Table 2.

Ordering options . . . . . . . . . . . . . . . . . . . . . . . .3

Table 3.

Pin multiplexing

. . . . . . . . . . . . . . . . . . . . . . . .5

Table 4.

EM783 pin description

. . . . . . . . . . . . . . . . . . .8

Table 5.

Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .25

Table 6.

Static characteristics . . . . . . . . . . . . . . . . . . . .26

Table 7.

Power consumption for individual analog

and digital blocks . . . . . . . . . . . . . . . . . . . . . . .31

Table 8.

POR and BOD circuit settling characteristics . .35

Table 9.

Power supply ramp characteristics . . . . . . . . .36

Table 10. Flash characteristics . . . . . . . . . . . . . . . . . . . . .38

Table 11. EEPROM characteristics . . . . . . . . . . . . . . . . .38

Table 12. Dynamic characteristic: external clock

(XTALIN or CLKIN pin) . . . . . . . . . . . . . . . . . .38

Table 13. Dynamic characteristic: IRC . . . . . . . . . . . . . . .39

Table 14. Dynamic characteristics: WDOsc and LFOsc. .39

Table 15. Dynamic characteristic: digital I/O pins[1] . . . . . 40

Table 16. Dynamic characteristic: I2C-bus pins[1] . . . . . . 40

Table 17. Dynamic characteristics of SSP pins in

SPI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Table 18. BOD static characteristics[1] . . . . . . . . . . . . . . . 44

Table 19. DAC static and dynamic characteristics . . . . . 45

Table 20. DAC sampling frequency range and power

consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 21. Internal voltage reference static and dynamic

characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 45

Table 22. Recommended values for CX1/CX2 in oscillation

mode (low frequency mode) . . . . . . . . . . . . . . 48

Table 23. Recommended values for CX1/CX2 in oscillation

mode (high frequency mode) . . . . . . . . . . . . . . 48

Table 24. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 53

Table 25. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 53

20. Figures

Fig 1.

EM783 block diagram . . . . . . . . . . . . . . . . . . . . . .4

Fig 2.

Pin configuration HVQFN33 package . . . . . . . . . .5

Fig 3.

EM783 memory map . . . . . . . . . . . . . . . . . . . . . .14

Fig 4.

EM783 clock generation block diagram . . . . . . . .21

Fig 5.

Active mode: Typical supply current IDD versus

temperature for different system clock frequencies

(all peripherals disabled) . . . . . . . . . . . . . . . . . . .29

Fig 6.

Active mode: Typical supply current IDD versus

temperature for different system clock frequencies

(all peripherals enabled) . . . . . . . . . . . . . . . . . . .30

Fig 7.

Sleep mode: Typical supply current IDDversus

temperature for different system clock frequencies

(all peripherals disabled) . . . . . . . . . . . . . . . . . . .30

Fig 8.

High-current source output driver: Typical

HIGH-level output voltage VOH versus

HIGH-level output current IOH . . . . . . . . . . . . . . .31

Fig 9.

High-current sink pins: Typical LOW-level output

current IOL versus LOW-level output voltage

VOL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

Fig 10. Typical LOW-level output current IOL versus

LOW-level output voltage VOL . . . . . . . . . . . . . . .32

Fig 11. Typical HIGH-level output voltage VOH versus

HIGH-level output source current IOH . . . . . . . . .33

Fig 12. Typical pull-up current Ipu versus input voltage

VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

Fig 13. Typical pull-down current Ipd versus input

voltage VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34

Fig 14. UVLO timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Fig 15. Power supply voltage profile . . . . . . . . . . . . . . . .37

Fig 16. External clock timing (with an amplitude

of at least Vi(RMS) = 200 mV) . . . . . . . . . . . . . . . .39

Fig 17. Internal IRC frequency vs. temperature . . . . . . . .39

Fig 18. I2C-bus pins clock timing . . . . . . . . . . . . . . . . . . .41

Fig 19. SSP master timing in SPI mode. . . . . . . . . . . . . .43

Fig 20. SSP slave timing in SPI mode . . . . . . . . . . . . . . .44

Fig 21. Typical internal voltage reference output voltage.46

Fig 22. Slave mode operation of the on-chip oscillator . . 47

Fig 23. Oscillation mode of operation and external crystal

model used for CX1/CX2 evaluation . . . . . . . . . . . 47

Fig 24. Standard I/O pad configuration . . . . . . . . . . . . . . 49

Fig 25. Reset pad configuration . . . . . . . . . . . . . . . . . . . 49

Fig 26. Functional diagram of the UVLO protection and

reset timer circuit. . . . . . . . . . . . . . . . . . . . . . . . . 50

Fig 27. Package outline HVQFN33 . . . . . . . . . . . . . . . . . 51

Fig 28. Reflow soldering of the HVQFN33(7x7) package 52

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