MPC750EC datasheet(36/44 Pages) NXP

36 / 44 page

MPC750A RISC Microprocessor Hardware Speciﬁcations

System Design Information

1.8.6 Pull-up Resistor Requirements

The MPC750 requires high-resistive (weak: 10 K

Ω) pull-up resistors on several control signals of the bus

interface to maintain the control signals in the negated state after they have been actively negated and

released by the MPC750 or other bus masters. These signals are TS, ABB, DBB, and ARTRY.

In addition, the MPC750 has one open-drain style output that requires a pull-up resistors (weak or

stronger: 4.7 K

Ω–10 KΩ) if it is used by the system. This signal is CKSTP_OUT.

During inactive periods on the bus, the address and transfer attributes on the bus are not driven by any

master and may ﬂoat in the high-impedance state for relatively long periods of time. Since the MPC750

must continually monitor these signals for snooping, this ﬂoat condition may cause excessive power draw

by the input receivers on the MPC750 or by other receivers in the system. It is recommended that these

signals be pulled up through weak (10 K

Ω) pull-up resistors or restored in some manner by the system.

The snooped address and transfer attribute inputs are A[0–31], AP[0–3], TT[0–4], TBST, and GBL.

The data bus input receivers are normally turned off when no read operation is in progress and do not

require pull-up resistors on the data bus. Other data bus receivers in the system, however, may require

pullups, or that those signals be otherwise driven by the system during inactive periods. The data bus

signals are

DH[0–31], DL[0–31], DP[0–7].

If address or data parity is not used by the system, and the respective parity checking is disabled through

HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and

should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity

checking should also be disabled through HID0, and all parity pins may be left unconnected by the system.

No pull-up resistors are normally required for the L2 interface.

1.8.7 Thermal Management Information

This section provides thermal management information for the ceramic ball grid array (CBGA) package

for air-cooled applications. Proper thermal control design is primarily dependent upon the system-level

design—the heat sink, airﬂow and thermal interface material. To reduce the die-junction temperature, heat

sinks may be attached to the package by several methods—adhesive, spring clip to holes in the

printed-circuit board or package, and mounting clip and screw assembly; see Figure 20. This spring force

should not exceed 5.5 pounds of force.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

IVE

D B

Y F

INC

MPC750EC Datasheet(PDF) 36 Page - NXP Semiconductors