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DSP96002UM/AD Datasheet(PDF) 8 Page - NXP Semiconductors |
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DSP96002UM/AD Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 111 page  Signal/Connection Descriptions Clock 1-4 DSP96002/D, Rev. 2 MOTOROLA CLOCK Table 1-4 Clock Signal Signal Name Type State During Reset Signal Description CLK Input Input Clock Input —CLK is a high frequency processor clock input. The frequency is twice the instruction rate. As shown in Figure 1-2, an internal phase generator divides CLK into four phases (t0, t1, t2 and t3), which is the basic instruction execution cycle. Additional tw phases are optionally generated to insert Wait States (WS) into instruction execution. A Wait State is formed by pairing a t2 and tw phase. CLK should be continuous with a 46– 54% duty cycle. Figure 1-2 Clock Input and Instruction Cycle Timing Two Wait States No Wait States t0 t1 t2 t3 tw t0 t1 t2 t2 t2 tw t3 CLK Instruction Cycle Instruction Cycle Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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