DSP96002UMSLASHAD datasheet(9/111 Pages) NXP

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Signal/Connection Descriptions

Interrupt and Mode Control

MOTOROLA

DSP96002/D, Rev. 2

1-5

INTERRUPT AND MODE CONTROL

Table 1-5

Interrupt and Mode Control

Signal Name

Type

State During

Reset

Signal Description

RESET

Input Input

Reset

—This input is a direct hardware reset of the

processor. When RESET is asserted low, the signal is

internally synchronized to the input clock (CLK), the DSP

is placed in the Reset state, and the internal phase

generator is reset. A Schmitt trigger input is used for

noise immunity and allows a slowly rising input (such as

a capacitor charging) to reliably reset the chip. If RESET is

deasserted synchronous to the input clock (CLK), exact

start-up timing is guaranteed, allowing multiple

processors to start-up synchronously and operate

together in “lock-step.” When the RESET pin is

deasserted, the initial chip operating mode is latched

from the MODA, MODB and MODC pins.

MODA/IRQA

Input Input

Mode Select A/External Interrupt Request A

—This

input is internally synchronized to the input clock (CLK).

MODA/IRQA selects the initial chip operating mode

during hardware reset and becomes a level-sensitive or

negative-edge-triggered, maskable interrupt request

input during normal instruction processing. MODA,

MODB and MODC select one of eight initial chip

operating modes latched into the Operating Mode

IRQA is asserted synchronous to the input clock (CLK),

multiple processors can be resynchronized by using the

WAIT instruction and asserting IRQA to exit the Wait

state. If the processor is in the Stop standby state and

IRQA is asserted, the processor will exit the Stop state.

MODB/ IRQB

Input Input

Mode Select B/External Interrupt Request B

—This input

is internally synchronized to the input clock (CLK).

MODB/IRQB selects the initial chip operating mode

during hardware reset and becomes a level-sensitive or

negative-edge-triggered, maskable interrupt request

input during normal instruction processing. MODA,

MODB and MODC select one of eight initial chip

operating modes latched into the Operating Mode

IRQB is asserted synchronous to the input clock (CLK),

multiple processors can be resynchronized by using the

WAIT instruction and asserting IRQB to exit the Wait

state.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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