DSP96002UMSLASHAD datasheet(11/111 Pages) NXP

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Signal/Connection Descriptions

Port A and Port B

MOTOROLA

DSP96002/D, Rev. 2

1-7

AD0–AD31

BD0–BD31

Input/

Output

Tri-stated

Data Bus

—D0–D31 are tri-state, active high, bidirectional

input/outputs whether the DSP is a bus master or not. The

Data Enable (DE) input acts as an output enable control for

D0–D31. As a bus master, the data lines are controlled by

the CPU instruction execution or the DMA controller. D0–

D31 are also the Host Interface data lines. If there is no

external bus activity, D0–D31 are tri-stated.

AS0–AS1

BS0–BS1

Output

Tri-stated

Space Select—

These signals can be viewed in different

ways, depending on how the external memories are

mapped. They support splitting memory spaces among

ports, and mapping multiple memory spaces into the same

physical memory locations. S0 and S1 are outputs when the

DSP is the bus master and tri-stated when the DSP is not a

bus master. Timing is the same as the address lines A0–

A31.

AR/W

BR/W

Input

Output

Tri-stated

Read/Write—

R/W is a an output when the DSP is the bus

master and an input when not a bus master. Bus master

timing is the same as the DSP96002 address lines, giving an

“early write” signal for DRAM interfacing. R/W is high for

a read access and low for a write access. The R/W pin is

also the Host Interface read/write input. As an input, R/W

may change asynchronously relative to the input clock.

R/W goes high if the external bus is not used during an

instruction cycle.

AWR

BWR

Output

Tri-stated

Write Strobe

—WR is an output when the DSP is the bus

master and tri-stated when it is not a bus master. WR

supports a glueless interface to external SRAMs. WR is

asserted during external memory write cycles to indicate

that the address lines A0–A32, S1, S0, BS, BL, and R/W are

stable. The output data goes to the data bus after WR is

asserted. WR requires a weak external pull-up resistor and

can be connected directly to the WE pin of a Static RAM.

ABS

BBS

Output

Tri-stated

Bus Strobe—

BS is an output when the DSP is the bus

master and tri-stated when it is not a bus master. Bus strobe

is asserted at the start of a bus cycle (providing an “early

bus start” signal for DRAM interfacing) and deasserted at

the end of the bus cycle. The early negation provides an

“early bus end” signal useful for external bus control. If the

external bus is not used during an instruction cycle, BS

remains deasserted until the next external bus cycle.

Table 1-6

Port A and Port B (Continued)

Signal

Name

Type

State

During

Reset

Signal Description

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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