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PCAL9714 Datasheet(PDF) 41 Page - NXP Semiconductors |
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PCAL9714 Datasheet(HTML) 41 Page - NXP Semiconductors |
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41 / 56 page  NXP Semiconductors PCAL9714 Ultra low-voltage translating 14-bit SPI I/O expander with Agile I/O features, interrupt output, and reset 12 Dynamic characteristics Guaranteed by design; over recommended operating free air temperature range, unless otherwise specified. See Figure 32 Conditions VDD(SPI) ≤ 1.65 V VDD(SPI) ≤ 5.5 V Symbol Parameter Min Max Min Max Unit fSCLK maximum input clock frequency - 2 - 5 MHz tLOW LOW period of the SCLK clock 250 - 100 - ns tHIGH HIGH period of the SCLK clock 250 - 100 - ns tDS SDIN to SCLK set-up time 20 - 20 - ns tDH SDIN to SCLK hold time 30 - 30 - ns tCSS CSn to SCLK rise set-up time 100 - 100 - ns tCS_HI minimum CSn deasserted HIGH time 200 - 200 - ns tCSH SCLK fall to CSn deasserted hold time 20 - 20 - ns tDIS(SDOUT) SDOUT disable time CL = 100 pF - 150 - 150 ns tV(SDOUT) SDOUT valid time CL = 100 pF - 200 - 200 ns Table 50. SPI bus interface timing requirements SCLK tLOW tHIGH 1 / fSCLK tCSS CS tDS tDH D23 D22 D21 SDI D2 D1 D0 tCSH tCS_HI D23 aaa-009240 Figure 31. Definition of timing Over recommended operating free air temperature range, unless otherwise specified. See Figure 34. SPI bus Symbol Parameter Conditions Min Max Unit tw(rst) reset pulse width 150 - ns trec(rst) reset recovery time 500 - ns trst reset time [1] 600 - ns Table 51. Reset timing requirements [1] Minimum time for SDOUT to become HIGH. PCAL9714 All information provided in this document is subject to legal disclaimers. © 2023 NXP B.V. All rights reserved. Product data sheet Rev. 1.0 — 1 May 2023 41 / 56 |
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