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PCAL9714 Datasheet(PDF) 1 Page - NXP Semiconductors |
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PCAL9714 Datasheet(HTML) 1 Page - NXP Semiconductors |
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1 / 56 page ![]() PCAL9714 Ultra low-voltage translating 14-bit SPI I/O expander with Agile I/O features, interrupt output, and reset Rev. 1.0 — 1 May 2023 Product data sheet 1 General description The PCAL9714 is a 14-bit general purpose I/O expander that provides remote I/O expansion for most microcontroller families via the Serial Peripheral Interface (SPI). The ultra low-voltage interface allows for direct connection with the microcontroller operating down to 1.1 V. NXP I/O expanders provide a simple solution when additional I/Os are needed while keeping interconnections to a minimum, for example, in battery-powered mobile applications for interfacing to sensors, push buttons, keypad, etc. In addition to providing a flexible set of GPIOs, it simplifies interconnection of a processor running at one voltage level down to 1.1 V to I/O devices operating at a different voltage level 1.65 V to 5.5 V. The PCAL9714 has built-in level shifting feature that makes these devices extremely flexible in mixed power supply systems where communication between incompatible I/O voltages is required, allowing seamless communications with next-generation low voltage microprocessors and microcontrollers on the interface side and peripherals at a higher voltage on the port side. There are two supply voltages for PCAL9714: VDD(SPI) and VDD(P). VDD(SPI) provides the supply voltage for the interface at the master side (for example, a microcontroller) and the VDD(P) provides the supply for core circuits and Port P. The bidirectional voltage level translation in the PCAL9714 is provided through VDD(SPI). VDD(SPI) should be connected to the VDD of the external SPI interface lines. This indicates the VDD level of the SPI to the PCAL9714, while the voltage level on Port P of the PCAL9714 is determined by the VDD(P). The PCAL9714 works with the SPI speed at 5 MHz and implements Agile I/O, which are additional features specifically designed to enhance the I/O. These additional features are: programmable output drive strength, latchable inputs, programmable pullup/pulldown resistors, maskable interrupt, interrupt status register, programmable open-drain or push-pull outputs. Additional Agile I/O Plus features include interrupts specified by level or edge, and they can be cleared individually without disturbing the other interrupt events. Also, switch debounce hardware is implemented. At power-on, the I/Os are configured as inputs. However, the system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each input or output is kept in the corresponding input or output register. The polarity of the Input Port register can be inverted with the Polarity Inversion register, saving external logic gates. Programmable pullup and pulldown resistors eliminate the need for discrete components. The system master can reset the PCAL9714 in the event of a time-out or other improper operation by asserting a LOW in the RESET input. The power-on reset puts the registers in their default state and initializes the SPI state machine. The RESET pin causes the same reset/initialization to occur without de-powering the part. The PCAL9714 open-drain interrupt (INT) output is activated when any input state differs from its corresponding Input Port register state and is used to indicate to the system master that an input state has changed. (INT) can be connected to the interrupt input of a microcontroller. By sending an interrupt signal on this line, the remote I/O can inform the microcontroller if there is incoming data on its ports without having to communicate via the SPI. Thus, the PCAL9714 can remain a simple slave device. The input latch feature holds or latches the input pin state and keeps the logic values that created the interrupt until the master can service the interrupt. This minimizes the host’s interrupt service response for fast moving inputs. |
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