PCAL9714 datasheet(6/56 Pages) NXP

6 / 56 page

NXP Semiconductors

PCAL9714

Ultra low-voltage translating 14-bit SPI I/O expander with Agile I/O features, interrupt output, and

reset

5 Pinning information

5.1 Pinning

aaa-042111

Transparent top view

P1_3

P0_4

P0_5

P1_4

P0_3

P1_5

P0_2

P0_1

SDOUT

P0_0

ADDR

terminal 1

index area

PCAL9714HN

1. The exposed center pad, if used, must be connected only as a secondary ground or must be left electrically open.

Figure 2. Pin configuration for HVQFN24

5.2 Pin description

Symbol

Description

INT

Interrupt output. Connect to VDD(SPI) or VDD(P) through a pullup resistor.

VDD(SPI)

Supply voltage of SPI bus. Connect directly to the VDD of the external SPI master.

Provides voltage-level translation.

RESET

Active LOW reset input. Connect to VDD(SPI) if no external logic signal is driving the

pin.

P0_0[1]

Port 0 input/output 0.

P0_1[1]

Port 0 input/output 1.

P0_2[1]

Port 0 input/output 2.

P0_3[1]

Port 0 input/output 3.

P0_4[1]

Port 0 input/output 4.

P0_5[1]

Port 0 input/output 5.

P0_6[1]

Port 0 input/output 6.

P0_7[1]

Port 0 input/output 7.

VSS

Ground.

P1_0[2]

Port 1 input/output 0.

P1_1[2]

Port 1 input/output 1.

P1_2[2]

Port 1 input/output 2.

P1_3[2]

Port 1 input/output 3.

P1_4[2]

Port 1 input/output 4.

Table 3. Pin description

PCAL9714

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.0 — 1 May 2023

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