DP83255AVF datasheet(24/96 Pages) NSC

24 / 96 page

50 Registers (Continued)

INTERRUPT CONDITION REGISTER (ICR)

The Interrupt Condition Register records the occurrence of an internal error event the detection of Line State an unsuccessful

write by the Control Bus Interface the expiration of an internal counter or the assertion of one or more of the User Definable

Sense pins

The Interrupt Condition Register will assert the Interrupt pin (INT) when one or more bits within the register are set to 1 and the

corresponding mask bits in the Interrupt Condition Mask Register (ICMR) are also set to 1

ACCESS RULES

ADDRESS

READ

WRITE

02h

Always

Conditional

UDI

RCB

RCA

LEMT

CWI

CCR

CPE

DPE

Bit

Symbol

Description

DPE

PHY

REQUEST

DATA PARITY ERROR

This bit will be set to 1 when

(1) The PHY Request Data Parity Enable bit (PRDPE) of the Current Transmit State Register

(CTSR) is set to 1 and

(2) The Transmitter Block detects a parity error in the incoming PHY Request Data

The source of the data can be from the PHY Invalid Bus the Receiver Bus the A

Bus or the

Bus of the Configuration Switch

CPE

CONTROL BUS DATA PARITY ERROR

This bit will be set to 1 when

(1) The Control Bus Parity Enable pin is asserted (CBPE e VCC) and

(2) The Control Bus Interface detects a parity error in the incoming Control Bus Data

(CBDk70l) during a write cycle

CCR

CONTROL BUS WRITE COMMAND REJECT

This bit will be set to 1 when an attempt to

write into one of the following read-only registers is made

Current Receive State Register (Register 08 CRSR)

Current Noise Count Register (Register 0F CNCR)

Current Noise Prescale Count Register (Register 10 CNPCR)

Current State Count Register (Register 13 CSCR)

Current State Prescale Count Register (Register 14 CSPCR)

Current Link Error Count Register (Register 16 CLECR)

Device ID Register (Register 18 IDR)

Current Injection Count Register (Register 19 CIJCR)

Reserved Register 0 (Register 1E RR0)

Reserved Register 1 (Register 1F RR1)

CWI

CONDITIONAL WRITE INHIBIT

Set to 1 when bits within mentioned registers do not match

bits in compare register This bit ensures that new (ie unread) data is not inadvertently

cleared while old data is being cleared through the Control Bus Interface

This bit is set to 1 to prevent the setting or clearing of any bit within the following registers

Interrupt Condition Register (Register 02 ICR)

Current Transmit State Register (Register 04 CTSR)

Receive Condition Register A (Register 09 RCRA)

Receive Condition Register B (Register 0A RCRB)

when they differ from the value of the corresponding bit in the following registers respectively

Interrupt Condition Compare Register (Register 1A ICCR)

Current Transmit State Compare Register (Register 1B CTSCR)

Receive Condition Compare Register A (Register 1C RCCRA)

Receive Condition Compare Register B (Register 1D RCCRB)

This bit must be cleared by software Note that this differs from the BMAC device bit of the

same name

DP83255AVF Datasheet(PDF) 24 Page - National Semiconductor (TI)

DP83255AVF Datasheet(HTML) 24 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

Datasheet Download

Link URL