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DP83255AVF Datasheet(PDF) 56 Page - National Semiconductor (TI) |
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DP83255AVF Datasheet(HTML) 56 Page - National Semiconductor (TI) |
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56 / 96 page ![]() 60 Pin Descriptions (Continued) TABLE 6-1 DP83251 Pinout Summary Pin No Signal Name Symbol IO ECLTTLOpen DrainPower 1 Control Bus Datak2l CBD2 IO TTL 2 Control Bus Datak3l CBD3 IO TTL 3 CMOS IO Ground GND a 0V 4 Control Bus Datak4l CBD4 IO TTL 5 Control Bus Datak5l CBD5 IO TTL 6 CMOS IO Power VCC a 5V 7 Control Bus Datak6l CBD6 IO TTL 8 Control Bus Datak7l CBD7 IO TTL 9 Control Bus Data Parity CBP IO TTL 10 Enable Pin 0 EP0 O TTL 11 Enable Pin 1 EP1 O TTL 12 CMOS Logic Ground GND a 0V 13 Control Bus Data Parity Enable CBPE I TTL 14 Sense Pin 0 SP0 I TTL 15 Sense Pin 1 SP1 I TTL 16 PHY Port A Indicate Parity AIP O TTL 17 PHY Port A Indicate Control AIC O TTL 18 PHY Port A Indicate Datak7l AID7 O TTL 19 PHY Port A Indicate Datak6l AID6 O TTL 20 CMOS IO Ground GND a 0V 21 PHY Port A Indicate Datak5l AID5 O TTL 22 CMOS IO Power VCC a 5V 23 PHY Port A Indicate Datak4l AID4 O TTL 24 CMOS Logic Ground GND a 0V 25 PHY Port A Indicate Datak3l AID3 O TTL 26 PHY Port A Indicate Datak2l AID2 O TTL 27 PHY Port A Indicate Datak1l AID1 O TTL 28 PHY Port A Indicate Datak0l AID0 O TTL 29 Cascade Start CS O TTL 30 Cascade Ready CR I Open Drain 31 No Connect NC 32 No Connect NC 33 Clock Detect CD I TTL 34 Signal Detect TTLSD I TTL 35 External Loopback Enable ELB O TTL 56 |
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