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DP83255AVF Datasheet(PDF) 51 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP83255AVF
Description  PLAYER Device (FDDI Physical Layer Controller)
PDF  96 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83255AVF Datasheet(HTML) 51 Page - National Semiconductor (TI)

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50 Registers (Continued)
INTERRUPT CONDITION COMPARISON REGISTER (ICCR)
The Interrupt Condition Comparison Register ensures that the Control Bus must first read a bit modified by the PLAYER device
before it can be written to by the Control Bus Interface
The current state of the Interrupt Condition Register (ICR) is automatically written into the Interrupt Condition Comparison
Register (ie ICCR e ICR) during a Control Bus Interface read-cycle of ICR
During a Control Bus Interface write-cycle the PLAYER device will set the Conditional Write Inhibit bit (CWI) of the Interrupt
Condition Register (ICR) to 1 and disallow the setting or clearing of a bit within ICR when the value of a bit in ICR differs from the
value of the corresponding bit in the Interrupt Condition Comparison Register
ACCESS RULES
ADDRESS
READ
WRITE
1Ah
Always
Always
D7
D6
D5
D4
D3
D2
D1
D0
UDIC
RCBC
RCAC
LEMTC
CWIC
CCRC
CPEC
DPEC
Bit
Symbol
Description
D0
DPEC
PHY
REQUEST DATA PARITY ERROR COMPARISON
The comparison
bit for the PHY
Request Data Parity Error bit (DPE) of the Interrupt Condition
Register (ICR)
D1
CPEC
CONTROL BUS DATA PARITY ERROR COMPARISON
The comparison bit
for the Control Bus Data Parity Error bit (CPE) of the Interrupt Condition
Register (ICR)
D2
CCRC
CONTROL BUS WRITE COMMAND REJECT COMPARISON
The
comparison bit for the Control Bus Write Command Reject bit (CCR) of the
Interrupt Condition Register (ICR)
D3
CWIC
CONDITIONAL WRITE INHIBIT COMPARISON
The comparison bit for the
Conditional Write Inhibit bit (CWI) of the Interrupt Condition Register (ICR)
D4
LEMTC
LINK ERROR MONITOR THRESHOLD COMPARISON
The comparison bit
for the Link Error Monitor Threshold bit (LEMT) of the Interrupt Condition
Register (ICR)
D5
RCAC
RECEIVE CONDITION A COMPARISON
The comparison bit for the
Receive Condition A bit (RCA) of the Interrupt Condition Register (ICR)
D6
RCBC
RECEIVE CONDITION B COMPARISON
The comparison bit for the
Receive Condition B bit (RCB) of the Interrupt Condition Register (ICR)
D7
UDIC
USER DEFINABLE INTERRUPT COMPARISON
The comparison bit for the
User Definable Interrupt bit (UDIC) of the Interrupt Condition Register (ICR)
51



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