| Electronic Components Datasheet Search |
|
DP83255AVF Datasheet(PDF) 46 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
DP83255AVF Datasheet(HTML) 46 Page - National Semiconductor (TI) |
|
46 / 96 page ![]() 50 Registers (Continued) LINK ERROR THRESHOLD REGISTER (LETR) The Link Error Threshold Register contains the start value for the Link Error Monitor Counter which is an 8-bit down-counter that decrements if link errors are detected When the Counter reaches 0 the Link Error Monitor Threshold Register value is loaded into the Link Error Monitor Counter and the Link Error Monitor Threshold bit (LEMT) of the Interrupt Condition Register (ICR) is set to 1 The Link Error Monitor Threshold Register value is also loaded into the Link Error Monitor Counter during every Control Bus Interface write-cycle of LETR The Counter is initialized to 0 during the reset process (ie RST e GND) ACCESS RULES ADDRESS READ WRITE 15h Always Always D7 D6 D5 D4 D3 D2 D1 D0 LET7 LET6 LET5 LET4 LET3 LET2 LET1 LET0 Bit Symbol Description D0 LET0 LINK ERROR THRESHOLD BIT k0l Least significant bit of the start value for the Link Error Monitor Counter D1–6 LET1–6 LINK ERROR THRESHOLD BIT k1–6l Intermediate bits of start value for the Link Error Monitor Counter D7 LET7 LINK ERROR THRESHOLD BIT k7l Most significant bit of the start value for the Link Error Monitor Counter 46 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |