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DP83255AVF Datasheet(PDF) 33 Page - National Semiconductor (TI) |
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DP83255AVF Datasheet(HTML) 33 Page - National Semiconductor (TI) |
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33 / 96 page  50 Registers (Continued) CURRENT RECEIVE STATE REGISTER (CRSR) (Continued) Bit Symbol Description D5 RES RESERVED Reserved for future use The reserved bit is set to 0 Note Users are discouraged from using this bit An attempt to write into this bit will cause the PLAYER device to ignore the CBUS write cycle and set the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1 D6 RES RESERVED Reserved for future use The reserved bit is set to 0 Note Users are discouraged from using this bit An attempt to write into this bit will cause the PLAYER device to ignore the CBUS write cycle and set the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1 D7 RES RESERVED Reserved for future use The reserved bit is set to 0 Note Users are discouraged from using this bit An attempt to write into this bit will cause the PLAYER device to ignore the CBUS write cycle and set the Control Bus Write Command Reject bit (CCR) of the Interrupt Condition Register (ICR) to 1 33 |
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