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DP83255AVF Datasheet(PDF) 70 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Part # DP83255AVF
Description  PLAYER Device (FDDI Physical Layer Controller)
PDF  96 Pages
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Manufacturer  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

DP83255AVF Datasheet(HTML) 70 Page - National Semiconductor (TI)

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60 Pin Descriptions (Continued)
SERIAL INTERFACE
The Serial Interface consists of IO signals used to connect the PLAYER device to the Physical Medium Dependent (PMD)
sublayer
The PLAYER device uses these signals to interface to a Fiber Optic Transmitter (FOTX) Fiber Optic Receiver (FORX) Clock
Recovery Device (CRD device) and Clock Distribution Device (CDD device)
Symbol
Pin No
IO
Description
CD
57
I
Clock Detect
A TTL input signal from the Clock Recovery Device indicating that the
Receive Clock (RXCg) is properly synchronized with the Receive Data (RXDg)
TTLSD
58
I
Signal Detect
A TTL input signal from the Clock Recovery Device indicating that a
signal is being received by the Fiber Optic Receiver
RXDa
63
I
Receive Data
Differential 100K ECL 125 Mbps serial data input signals from the Clock
Recovery Device
RXDb
64
TXDa
69
O
Transmit Data
Differential 100K ECL 125 Mbps serial data output signals to the Fiber
Optic Transmitter
TXDb
70
ELB
59
O
External Loopback Enable
A TTL output signal to the Clock Recovery Device which
enablesdisables loopback data through the Clock Recovery Device This signal is
controlled by the Mode Register
LBDa
66
O
Loopback Data
Differential 100K ECL 125 Mbps serial external loopback data output
signals to the Clock Recovery Device
LBDb
67
When the PLAYER device is not in external loopback mode the LBDa signal is kept
high and the LBDb signal is kept low
TEL
77
I
FOTX Enable Level
A TTL input signal to select the Fiber Optic Transmitter Enable
(TXE) signal level
TXE
86
O
FOTX Enable
A TTL output signal to enabledisable the Fiber Optic Transmitter The
output level of the TXE pin is determined by three parameters the Transmit Enable (TE)
bit in the Mode Register the TM2 – TM0 bits in the Current Transmit State Register and
also the input to the TEL pin
The following rules summarizes the output of the TXE pin
(1) If TE e 0 and TEL e GND then TXE e VCC
(2) If TE e 0 and TEL e VCC then TXE e GND
(3) If TE e 1 and OTM and TEL e GND then TXE e VCC
(4) If TE e 1 and OTM and TEL e VCC then TXE e GND
(5) If TE e 1 and not OTM and TEL e GND then TXE e GND
(6) If TE e 1 and not OTM and TEL e VCC then TXE e VCC
70



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