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DP83255AVF Datasheet(PDF) 62 Page - National Semiconductor (TI) |
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DP83255AVF Datasheet(HTML) 62 Page - National Semiconductor (TI) |
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62 / 96 page  60 Pin Descriptions (Continued) CLOCK INTERFACE The Clock Interface consists of 125 MHz and 125 MHz clocks used by the PLAYER device The clocks are generated by either the Clock Distribution Device or Clock Recovery Device Symbol Pin No IO Description LBC 57 I Local Byte Clock A TTL 125 MHz 50% duty cycle input clock from the Clock Distribution Device The Local Byte Clock is used by the PLAYER device’s internal CMOS logic and to latch incomingoutgoing data of the Control Bus Interface Port A Interface Port B Interface and other miscellaneous IOs RXCa 36 I Receive Bit Clock Differential 100k ECL 125 MHz clock input signals from the Clock Recovery Device The Receive Bit Clock is used by the Serial Interface to latch the RXC b 37 Receive Data (RXDg) TXCa 48 I Transmit Bit Clock Differential 100k ECL 125 MHz clock input signals from the Clock Distribution Device The Transmit Bit Clock is used by the Serial Interface to latch the TXCb 49 Transmit Data (TXDg) TBCa 51 I Transmit Byte Clock Differental 100k ECL 125 MHz clock input signals from the Clock Distribution Device The Transmit Byte Clock is used by the PLAYER device’s internal TBCb 52 Shift Register Block 62 |
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