DSP56721 datasheet(21/54 Pages) NXP

Part #	DSP56721

Description	Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors

PDF	54 Pages

Scroll/Zoom	100%

Manufacturer	NXP [NXP Semiconductors]

Direct Link	http://www.nxp.com

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Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

Freescale Semiconductor

Figure 15. SPI Master Timing Diagram (CPHA = 0)

HREQ in deassertion to last SCK sampling

edge (HREQ in set-up time) (CPHA = 1)

Master

—

First SCK edge to HREQ in not asserted

(HREQ in hold time)

Master

—

HREQ assertion width

Master

—

3.0

× TC

—

Notes:

1.VCORE_VDD = 1.0± 0.10 V; TJ = –40°C to 100°C; CL = 50 pF.

2. Pejriodically sampled, not 100% tested.

3. All times assume noise free inputs.

4. All times assume internal clock frequency of 200 MHz.

5. SHI_1 specs match those of SHI.

Table 8. Serial Host Interface SPI Protocol Timing Parameters (Continued)

No.

Characteristics1,3,4

Mode

Filter Mode

Expression

Min

Max

Unit

(Input)

SCK (CPOL = 0)

(Output)

SCK (CPOL = 1)

(Output)

MISO

(Input)

MOSI

(Output)

HREQ

(Input)

MSB

LSB

Valid

MSB

Valid

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