DSP56721 datasheet(26/54 Pages) NXP

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Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

Freescale Semiconductor

2.12

Programming the SHI I2C Serial Clock

The programmed serial clock cycle, TI2CCP, is specified by the value of the HDM[7:0] and HRS bits of the HCKR (SHI clock

control register).

The expression for T I2CCP is

T I2CCP = [TC × 2 × (HDM[7:0] + 1) × (7 × (1 — HRS) + 1)]

Eqn. 4

where

— HRS is the pre scaler rate select bit. When HRS is cleared, the fixed

divide-by-eight pre scaler is operational. When HRS is set, the pre scaler is bypassed.

— HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00 to $FF) may be

selected.

In I

2C mode, the user may select a value for the programmed serial clock cycle from

× TC (if HDM[7:0] = $02 and HRS = 1)

Eqn. 5

4096

× TC (if HDM[7:0] = $FF and HRS = 0)

Eqn. 6

The programmed serial clock cycle (TI2CCP) should be chosen in order to achieve the desired SCL serial clock cycle (TSCL), as

shown in Equation 4.

TI2CCP + 3 × TC + 45ns + TR

(Nominal, SCL Serial Clock Cycle (TSCL) generated as master)

Eqn. 7

HREQ in assertion to first SCL edge

• Filters bypassed

• Very Narrow filters enabled

• Narrow filters enabled

• Wide filters enabled

TAS;RQI

4327

4317

4282

4227

—

927

917

877

827

—

First SCL edge to HREQ is not asserted

(HREQ in hold time.)

tHO;RQI

0.0

—

0.0

—

Notes:

1. VCORE_VDD = 1.00± 0.10 V; TJ = –40°C to 100°C; CL = 50 pF.

2. Pull-up resistor: R P (min) = 1.5k

Ω.

3. Capacitive load: C b (max) = 50 pF.

4. All times assume noise free inputs.

5. All times assume internal clock frequency of 200 MHz.

6. SHI_1 specs match those of SHI.

7. Master Mode

Table 9. SHI I2C Protocol Timing Parameters (Continued)

Standard I2C

No.

Characteristics1,2,3,4,5

Symbol/

Expression

Standard

Fast-Mode

Unit

Min

Max

Min

Max

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