DSP56721 datasheet(32/54 Pages) NXP

32 / 54 page

Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

Freescale Semiconductor

Figure 23. ESAI HCKR Timing

2.14

Timer Timing

Table 11 lists the timer timing parameters and Figure 24 shows the timing diagram.

Figure 24. TIO Timer Event Input Restrictions Diagram

2.15

GPIO Timing

Table 12 lists the general purpose input and output (GPIO) timing and Figure 25 shows the timing diagram.

Table 11. Timer Timing Parameters

No.

Characteristics

Expression

Unit

Min

Max

TIO Low

× TC + 2.0

12.0

—

TIO High

× TC + 2.0

12.0

—

Notes:

1. VCORE_VDD = 1.00 V ± 0.10 V; TJ = –40°C to 100°C, CL = 50 pF

2. TIMER_1 specs match those of TIMER

Table 12. GPIO Timing Parameters

No.

Characteristics1

Expression

Min

Max

Unit

100

Fsys edge to GPIO out valid (GPIO out delay time)2

——

101

Fsys edge to GPIO out not valid (GPIO out hold time)2

——

102

Fsys In valid to EXTAL edge (GPIO in set-up time)2

—2

—

103

Fsys edge to GPIO in not valid (GPIO in hold time)2

—0

—

104

Minimum GPIO pulse high width

× TC

—

HCKR

SCKR

(Output)

TIO

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