DSP56721 datasheet(10/54 Pages) NXP

10 / 54 page

Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

Freescale Semiconductor

PD = 1.1 V × 625 mA

= 0.6875 W

TJ = 70 + (0.6875 × 40)

= 97.5° C

2.3

Power Requirements

To prevent high current conditions due to possible improper sequencing of the power supplies, use an external Schottky diode

as shown in Figure 6, connected between the DSP56720/DSP56721 IO_VDD and Core_VDD power pins.

Figure 6. Prevent High Current Conditions by Using External Schottky Diode

If an external Schottky diode is not used (to prevent a high current condition at power-up), then IO_VDD must be applied ahead

of Core_VDD, as shown in Figure 7.

Figure 7. Prevent High Current Conditions by Applying IO_VDD Before Core_VDD

For correct operation of the internal power-on reset logic, the Core_VDD ramp rate (Tr) to full supply must be less than 10 ms,

as shown in Figure 8.

There are no power down requirement for the digital 1.0 V (CORE) and 3.3 V (IO). For the analog PLL power, the digital (IO)

3.3 V must be power up before the analog 3.3 V power. Similarly, for power down the digital (IO) 3.3 V must be power down

after the analog power 3.3 V. This requirement is for avoiding possible leakage.

Figure 8. Ensure Correct Operation of Power-On Reset with Fast Ramp of Core_VDD

IO_VDD

Core_VDD

External

Schottky

Diode

Core_VDD

IO_VDD

Core_VDD

Tr must be < 10 ms

0 V

1.0 V

DSP56721 Datasheet(PDF) 10 Page - NXP Semiconductors