DSP56721 datasheet(46/54 Pages) NXP

46 / 54 page

Symphony™ DSP56720/DSP56721 Multi-Core Audio Processors, Rev. 5

Freescale Semiconductor

Figure 39. EMC Signals (EMC PLL Bypassed; LRCC[CLKDIV] = 4)

Table 19. EMC Timing Parameters (EMC PLL Bypassed; LRCC[CLKDIV] = 8)

Parameter

Symbol

Min

Max

Unit

LCLK cycle time

Tclk

—

Input setup to LCLK (except LGTA/LUPWAIT)

Tin_s

8—

Input hold from LCLK (except LGTA/LUPWAIT)1

Tin_h

–1

—

LGTA valid time

Tgta

—

LUPWAIT valid time

Tupwait

—

LALE negedge to LAD (address phase) invalid (address latch hold time)

Tale_h

5—

LALE valid time

Tale

—

Output setup from LCLK (except LAD[23:0] and LALE)

Tout_s

—

Output hold from LCLK (except LAD[23:0] and LALE)

Tout_h

—

Tin_s

Tin_h

LGTA

asynchronous input

LA[2:0]/LBCTL/LCS[7:0]

LOE/LWE

LCKE/LSDA10/LSDDQM

LGPL[5:0]

Output Signals

LCLK

LAD[23:0] (data)

Tclk

LUPWAIT

asynchronous input

Tgta

Tupwait

Tout_s

Tout_h

LALE

Tad_s

Tad_h

LAD[23:0]

Tad_z

LSDWE/LSDRAS/LSDCAS

Tale

Tale_h

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