AD7764 datasheet(5/21 Pages) AD

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Preliminary Technical Data

AD7764

Rev. PrC | Page 5 of 21

TIMING SPECIFICATIONS

Table 2.

AVDD1 = DVDD = 2.5 V, AVDD2 = AVDD3 = AVDD4 = 5 V, VREF = 4.096 V, TA = +25°C, CLOAD = 25pF.

Parameter

Limit at TMIN, TMAX

Unit

Description

fMCLK

500

KHz min

Applied Master Clock Frequency

MHz max

fICLK

250

kHz min

Internal Modulator Clock Derived from MCLK.

MHz max

1 × tICLK

typ

SCO High Period

1 × tICLK

typ

SCO Low Period

TBD

typ

SCO rising edge to FSO falling edge

TBD

typ

Data Access time, FSO falling edge to data active

TBD

ns max

Initial Data Access Time, SDO active to SDO valid

TBD

ns min

SDO valid to SCO Rising Edge

TBD

ns max

SCO rising edge to SDO valid

TBD

typ

SCO rising edge to FSO rising edge

TBD

typ

FSO rising edge to SDO invalid

t10

TBD × tSCO

max

FSO Low Period

t11

TBD

min

FSI Low Period

t121

TBD

max

FSI Low Period

t13

TBD

min

SCO rising edge to SDI valid

t14

TBD

min

SDI valid to SCO rising edge

t15

TBD

max

SCO rising edge to SDI valid

t16

TBD

min

FSI rising edge to SDI three-state

1 This is the max time FSI can be held low when writing to an individual (non-daisy chained) AD7764 device.

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