AD7764 datasheet(12/21 Pages) AD

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AD7764

Preliminary Technical Data

Rev. PrC | Page 12 of 21

THEORY OF OPERATION

The AD7764 employs a sigma-delta conversion technique to

convert the analog input into an equivalent digital word. The

modulator samples the input waveform and outputs an

equivalent digital word to the digital filter at a rate equal to I

CLK.

Due to the high over-sampling rate, which spreads the

quantization noise from 0 to f

ICLK, the noise energy contained in

the band of interest is reduced (Figure 12). To further reduce

the quantization noise, a high order modulator is employed to

shape the noise spectrum; so that most of the noise energy is

shifted out of the band of interest (Figure 13).

The digital filtering which follows the modulator removes the

large out-of-band quantization noise (Figure 14) while also

reducing the data rate from f

ICLK at the input of the filter to

ICLK/64 or less at the output of the filter, depending on the

decimation rate used.

Digital filtering has certain advantages over analog filtering. It

does not introduce significant noise or distortion and can be

made perfectly linear phase.

The AD7764 employs three Finite Impulse Response (FIR)

filters in series. By using different combinations of decimation

ratios, data can be obtained from the AD7764 at three data

rates. The first filter receives data from the modulator at ICLK

MHz where it is decimated by four to output data at (ICLK/4)

MHz.

QUANTIZATION NOISE

fICLK/2

BAND OF INTEREST

Figure 12. Σ-∆ ADC, Quantization Noise

fICLK/2

NOISE SHAPING

BAND OF INTEREST

Figure 13. Σ-∆ ADC, Noise Shaping

fICLK/2

BAND OF INTEREST

DIGITAL FILTER CUTOFF FREQUENCY

Figure 14 Σ-∆ ADC, Digital Filter Cutoff Frequency

The second filter allows the decimation rate to be chosen from

8x to 32x. The third filter has a fixed decimation rate of 2x.

Table 5 below shows some characteristics of the digital filtering

(See Clocking the AD7764 for details on ICLK).The group delay

of the filter is defined to be the delay to the centre of the

impulse response and is equal to the computation + filter

delays. The delay until valid data is available (the DVALID

status bit is set) is equal to 2x the filter delay + the computation

delay.

Table 5. Configuration With Default Filter

ICLK

Frequency

Decimation

Rate

Data State

Computation

Delay

Filter

Delay

Passband

Bandwidth

Output Data Rate

(ODR)

20 MHz

64x

Fully Filtered

2.25µS

87.6µS

125 kHz

312.5 kHz

20 MHz

128x

Fully Filtered

3.1µS

174µS

62.5 kHz

156.25 kHz

20 MHz

256x

Fully Filtered

4.65µS

346.8µS

31.25 kHz

78.125 kHz

12.288MHz

64x

Fully Filtered

3.66µS

142.6µS

76.8 kHz

192 kHz

12.288MHz

128x

Fully Filtered

5.05µS

283.2µS

38.4 kHz

96 kHz

12.288MHz

256x

Fully Filtered

7.57µS

564.5µS

19.2 kHz

48 kHz

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