ADS7066 datasheet(8/48 Pages) TI

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6.6 Timing Requirements

at AVDD = 3 V to 5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum

values at TA = –40°C to +125°C; typical values at TA = 25°C.

MIN

MAX

UNIT

CONVERSION CYCLE

fCYCLE

Sampling frequency

250

kSPS

tCYCLE

ADC cycle-time period

1/fCYCLE

tQUIET

Quiet acquisition time

tACQ

Acquisition time

Acquisition

time

800

tWH_CSZ

Pulse duration: CS high

220

tWL_CSZ

Pulse duration: CS low

210

SPI INTERFACE TIMINGS

fCLK

Maximum SCLK frequency

MHz

tCLK

Minimum SCLK time period

16.67

tPH_CK

SCLK high time

0.45

0.55

tCLK

tPL_CK

SCLK low time

0.45

0.55

tCLK

tSU_CSCK

Setup time: CS falling to the first SCLK capture edge

tSU_CKDI

Setup time: SDI data valid to the SCLK capture edge

6.4

tHT_CKDI

Hold time: SCLK capture edge to data valid on SDI

tD_CKCS

Delay time: last SCLK falling to CS rising

0.8

6.7 Switching Characteristics

at AVDD = 3 V to 5.5 V, DVDD = 1.65 V to 5.5 V, and maximum throughput (unless otherwise noted); minimum and maximum

values at TA = –40°C to +125°C; typical values at TA = 25°C.

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

CONVERSION CYCLE

tCONV

ADC conversion time

3200

RESET

tPU

Power-up time for device

AVDD ≥ 3 V

tRST

Delay time; RST bit = 1b to device reset

complete(1)

SPI INTERFACE TIMINGS

tDEN_CSDO

Delay time: CS falling to data enable

tDZ_CSDO

Delay time: CS rising to SDO going Hi-Z

tD_CKDO

Delay time: SCLK launch edge to (next)

data valid on SDO

(1)

RST bit is automatically reset to 0b after tRST.

ADS7066

SBAS928B – FEBRUARY 2020 – REVISED MAY 2023

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