ADS7066 datasheet(24/48 Pages) TI

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7.3.10.3.2 Register Read

A register read operation consists of two SPI frames: the first SPI frame initiates a register read and the second

SPI frame reads data from the register address provided in the first frame. As shown in Figure 7-10, the read

command (0001 0000b), the 8-bit register address, and the 8-bit dummy data are sent over the SDI pin during

the first 24-bit frame. On the rising edge of CS, the read command is decoded and the requested register data

are available for reading during the next frame. During the second frame, the first eight bits on SDO correspond

to the requested register read. During the second frame, SDI can be used to initiate another operation or can be

set to 0.

SCLK

SDO

0001 0000b

(RD_REG)

SDI

8-bit Address

0000 0000b

8-bit Register Data

Command

8-bit Address

8-bit Data

Optional; can set SDI = 0

Figure 7-10. Register Read Operation

7.3.10.3.2.1 Register Read With CRC

A register read consists of two SPI frames, as described in the Register Read section. When the CRC module is

enabled during a register read, as shown in Figure 7-11, the device appends an 8-bit output CRC byte along with

8-bit register data. The output CRC is computed by the device on the 8-bit register data.

SCLK

SDO

0001 0000b

(RD_REG)

SDI

8-bit

Address

NOP (SDI = 0)

Input

CRC[7:0]

0000

0000b

Input

CRC[7:0]

Data

Output

CRC[7:0]

Data Payload (24 bit)

Input CRC is calculated

on 24 bit payload

Data Payload (8 bit)

Output CRC is calculated on 8 bit payload

Data Payload (24 bit)

Input CRC is calculated

on 24 bit payload

Figure 7-11. Register Read With CRC

ADS7066

SBAS928B – FEBRUARY 2020 – REVISED MAY 2023

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