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ADS7066 Datasheet(PDF) 21 Page - Texas Instruments |
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ADS7066 Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 48 page ![]() Table 7-4. Output Data Frames CRC_EN OSR[2:0] APPEND_STATUS[1:0] OUTPUT DATA FRAME DAISY-CHAIN MODE CRC module disabled (CRC_EN = 0) No averaging No flags (00b or 11b) {Conversion result [15:0], 8'b0} Supported Channel ID (01b) {Conversion result [15:0], CHID[3:0], 4'b0} Supported Status flags (10b) {Conversion result [15:0], status flags[3:0], 4'b0} Supported Averaging enabled No flags (00b or 11b) {Conversion result [19:0], 4'b0} Supported Channel ID (01b) {Conversion result [19:0], CHID[3:0]} Supported Status flags (10b) {Conversion result [19:0], status flags[3:0]} Supported CRC module enabled (CRC_EN = 1) No averaging No flags (00b or 11b) {Conversion result [15:0], CRC[7:0], 8'b0} Supported Channel ID (01b) {Conversion result [15:0], CHID[3:0], 4'b0, CRC[7:0]} Not supported Status flags (10b) {Conversion result [15:0], status flags[3:0], 4'b0, CRC[7:0]} Not supported Averaging enabled No flags (00b or 11b) {Conversion result [19:0], 4'b0, CRC[7:0]} Not supported Channel ID (01b) {Conversion result [19:0], CHID[3:0], CRC[7:0]} Not supported Status flags (10b) {Conversion result [19:0], status flags[3:0], CRC[7:0]} Not supported 7.3.10 Device Programming 7.3.10.1 Enhanced-SPI Interface The device features an enhanced-SPI interface that allows the host controller to operate at slower SCLK speeds and still achieve full throughput. As described in Table 7-5, the host controller can use any of the four SPI-compatible protocols (SPI-00, SPI-01, SPI-10, or SPI-11) to access the device. Table 7-5. SPI Protocols for Configuring the Device PROTOCOL SCLK POLARITY (At the CS Falling Edge) SCLK PHASE (Capture Edge) CPOL_CPHA[1:0] DIAGRAM SPI-00 Low Rising 00b Figure 7-5 SPI-01 Low Falling 01b Figure 7-6 SPI-10 High Falling 10b Figure 7-5 SPI-11 High Rising 11b Figure 7-6 On power-up, the device defaults to the SPI-00 protocol for data read and data write operations. To select a different SPI-compatible protocol, program the CPOL_CPHA[1:0] field. This first write operation must adhere to the SPI-00 protocol. Any subsequent data transfer frames must adhere to the newly-selected protocol. SCLK SDO MSB MSB-1 MSB-2 LSB+1 LSB CPOL = 0 CPOL = 1 CS Figure 7-5. Standard SPI Timing Protocol (CPHA = 0) SCLK SDO 0 MSB MSB-1 LSB+1 LSB CPOL = 0 CPOL = 1 CS Figure 7-6. Standard SPI Timing Protocol (CPHA = 1) www.ti.com ADS7066 SBAS928B – FEBRUARY 2020 – REVISED MAY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: ADS7066 |
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