LP5860 datasheet(16/71 Pages) TI

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Frame N-1

Frame N

Figure 8-4. On Demand Data Refresh – Mode 1

Mode 2: 8-bit PWM data with VSYNC command. Data is held and sent out simultaneously by frame after

receiving the VSYNC command.

Mode 3: 16-bit PWM data with VSYNC command. Data is held and sent out simultaneously by frame after

receiving the VSYNC command.

Frame control is implemented in Mode 2 and Mode 3. Instead of refreshing the output instantly after data

is received (Mode 1), the device holds the data and refreshes the whole frame data by a fixed frame rate,

fVSYNC. Usually, 24 Hz, 50 Hz, 60 Hz, 120 Hz or even higher frame rate is selected to achieve vivid animation

effects. Whole SRAM Data Refresh is shown in Figure 8-5, a new frame is updated after receiving the VSYNC

command.

Frame N-1

Frame N

Figure 8-5. Whole SRAM Data Refresh

Comparing with Mode 1, Mode 2 and Mode 3 provide a better synchronization when multiple LP5861T devices

used together. A high-level pulse width longer than tSYNC_H is required at the beginning of each VSYNC frame.

Figure 8-6 shows the VSYNC connections and Figure 8-7 shows the timing requirements.

MCU

LP586x

GPIO

SYNC

Figure 8-6. Multiple Devices Sync

fVSYNC

t>tVSYNC_H

Figure 8-7. VSYNC Timing

Table 8-4 is the summary of the three data refresh modes.

Table 8-4. Data Refresh Mode

MODE TYPE

PWM RESOLUTION

PWM OUTPUT

EXTERNAL VSYNC

Mode 1

8 bits

Data update instantly

LP5861T

SNVSCE4 – MAY 2023

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LP5860 Datasheet(PDF) 16 Page - Texas Instruments