SLG47502V datasheet(37/192 Pages) RENESAS

37 / 192 page

Datasheet

28-Feb-2023

CFR0011-120-00

Revision 2.3

37 of 194

SLG47512/13

Low Voltage GreenPAK Programmable

Mixed-Signal Matrix

Preliminary

6.2 MATRIX OUTPUT TABLE

Table 21: Matrix Output Table

Address

Matrix Output Signal Function

Matrix Output

Number

[45:40]

IN0 of LUT2_0 or Clock Input of DFF0 or Clock Input of Shift_Reg0

[51:46]

IN1 of LUT2_0 or Data Input of DFF0 or Data Input of Shift_Reg0

[57:52]

IN0 of LUT2_1 or Clock Input of DFF1 or Clock Input of Shift_Reg1

[63:58]

IN1 of LUT2_1 or Data Input of DFF1 or Data Input of Shift_Reg1

[69:64]

IN0 of LUT2_2 or Clock Input of DFF2 or Clock Input of Shift_Reg2

[75:70]

IN1 of LUT2_2 or Data Input of DFF2 or Data Input of Shift_Reg2

[81:76]

IN0 of LUT2_3 or Clock Input of PGen

[87:82]

IN1 of LUT2_3 or nRST of PGen

[93:88]

IN0 of LUT3_0 or Clock Input of DFF3 or Clock Input of Shift_Reg3

[99:94]

IN1 of LUT3_0 or Data Input of DFF3 or Data Input of Shift_Reg3

[105:100]

IN2 of LUT3_0 or nRST(nSET) of DFF3 or nRST(nSET) of Shift_Reg3

[111:106]

IN0 of LUT3_1 or Clock Input of DFF4 or Clock Input of Shift_Reg4

[117:112]

IN1 of LUT3_1 or Data Input of DFF4 or Data Input of Shift_Reg4

[123:118]

IN2 of LUT3_1 or nRST(nSET) of DFF4 or nRST(nSET) of Shift_Reg4

[129:124]

IN0 of LUT3_2 or Clock Input of DFF5 or Clock Input of Shift_Reg5

[135:130]

IN1 of LUT3_2 or Data Input of DFF5 or Data Input of Shift_Reg5

[141:136]

IN2 of LUT3_2 or nRST(nSET) of DFF5 or nRST(nSET) of Shift_Reg5

[147:142]

IN0 of LUT3_3 or Clock Input of DFF6 or Clock Input of Shift_Reg6

[153:148]

IN1 of LUT3_3 or Data Input of DFF6 or Data Input of Shift_Reg6

[159:154]

IN2 of LUT3_3 or nRST(nSET) of DFF6 or nRST(nSET) of Shift_Reg6

[165:160]

IN0 of LUT3_4 or Clock Input of DFF7 or Clock Input of Shift_Reg7

[171:166]

IN1 of LUT3_4 or Data Input of DFF7 or Data Input of Shift_Reg7

[177:172]

IN2 of LUT3_4 or nRST(nSET) of DFF7 or nRST(nSET) of Shift_Reg7

[183:178]

IN0 of LUT3_5 or Clock Input of DFF8 or Clock Input of Shift_Reg8

[189:184]

IN1 of LUT3_5 or Data Input of DFF8 or Data Input of Shift_Reg8

[195:190]

IN2 of LUT3_5 or nRST(nSET) of DFF8 or nRST(nSET) of Shift_Reg8

[201:196]

IN0 of LUT3_6 or Clock Input of DFF9 or Clock Input of Shift_Reg9

[207:202]

IN1 of LUT3_6 or Data Input of DFF9 or Data Input of Shift_Reg9

[213:208]

IN2 of LUT3_6 or nRST(nSET) of DFF9 or nRST(nSET) of Shift_Reg9

[219:214]

IN0 of LUT3_7 or Clock Input of DFF10 or Clock Input of Shift_Reg10

[225:220]

IN1 of LUT3_7 or Data Input of DFF10 or Data Input of Shift_Reg10

[231:226]

IN2 of LUT3_7 or nRST(nSET) of DFF10 or nRST(nSET) of Shift_Reg10

[237:232]

IN0 of LUT3_8 or Clock Input of DFF11 or Clock Input of Shift_Reg11

[243:238]

IN1 of LUT3_8 or Data Input of DFF11 or Data Input of Shift_Reg11

[249:244]

IN2 of LUT3_8 or nRST(nSET) of DFF11 or nRST(nSET) of Shift_Reg11

[255:250]

IN0 of LUT3_9 or Clock Input of DFF12 or Clock Input of Shift_Reg12

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