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SLG47502V Datasheet(PDF) 20 Page - Renesas Technology Corp |
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SLG47502V Datasheet(HTML) 20 Page - Renesas Technology Corp |
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20 / 192 page  Datasheet 28-Feb-2023 CFR0011-120-00 Revision 2.3 20 of 194 © 2023 Renesas Electronics Corporation SLG47512/13 Low Voltage GreenPAK Programmable Mixed-Signal Matrix Preliminary tpd Delay Digital Input with Schmitt Trigger to PP 1x 18 18 12 12 8 8 7 7 ns tpd Delay Low Voltage Digital Input to PP 1x 18 18 12 12 8 8 7 7 ns tpd Delay Digital input to NMOS 1x -- 18 -- 12 -- 8 -- 7 ns tpd Delay Digital input to NMOS 2x -- 18 -- 12 -- 8 -- 7 ns tpd Delay Output enable from Pin, OE Hi-Z to 1 19 -- 12 -- 10 -- 9 -- ns tpd Delay Output enable from Pin, OE Hi-Z to 0 -- 19 -- 12 -- 10 -- 9 ns tpd Delay PP 1x 3 State Hi-Z to 1 19 -- 12 -- 10 -- 9 -- ns tpd Delay PP 1x 3 State Hi-Z to 0 -- 19 -- 12 -- 10 -- 9 ns tpd Delay PP 2x 3 State Hi-Z to 1 19 -- 11 -- 10 -- 9 -- ns tpd Delay PP 2x 3 State Hi-Z to 0 -- 19 -- 11 -- 10 -- 9 ns tpd Delay LATCH Q 13 13 8 8 5 5 4 4 ns tpd Delay LATCH nQ 13 13 8 8 5 5 4 4 ns tpd Delay LATCH nRESET High Q 13 13 8 8 5 5 4 4 ns tpd Delay LATCH nRESET High nQ 13 13 8 8 5 5 4 4 ns tpd Delay LATCH nRESET Low Q 13 13 8 8 5 5 4 4 ns tpd Delay LATCH nRESET Low nQ 13 13 8 8 5 5 4 4 ns tpd Delay LATCH nSET High Q 13 13 8 8 5 5 4 4 ns tpd Delay LATCH nSET High nQ 13 13 8 8 5 5 4 4 ns tpd Delay LATCH nSET Low Q 14 13 10 10 6 6 4 4 ns tpd Delay LATCH nSET Low nQ 14 13 10 9 6 6 4 4 ns tpd Delay Multi-Function LATCH Q 13 13 9 9 6 6 4 4 ns tpd Delay Multi-Function LATCH nQ 13 13 9 9 6 6 4 4 ns tpd Delay Multi-Function LATCH nRESET Q 13 13 9 9 6 6 4 4 ns tpd Delay Multi-Function LATCH nRESET nQ 13 13 9 9 6 6 4 4 ns tpd Delay Multi-Function LATCH nSET Q 13 13 9 9 6 6 4 4 ns tpd Delay Multi-Function LATCH nSET nQ 13 13 9 9 6 6 4 4 ns tpd Delay 2-bit LUT 13 13 6 6 6 6 4 4 ns tpd Delay 3-bit LUT 13 13 9 8 6 6 4 4 ns tpd Delay 4-bit LUT 13 13 8 8 6 6 4 4 ns tpd Delay Multi-Function 3-bit LUT 13 13 9 9 6 6 4 4 ns tpd Delay Multi-Function 3-bit LUT, CNT Delay 13 13 9 9 6 6 4 4 ns tpd Delay Multi-Function 4-bit LUT 13 13 9 9 6 6 4 4 ns tpd Delay Multi-Function 4-bit LUT, CNT Delay 13 13 9 9 6 6 4 4 ns tpd Delay Edge detect 10 10 5 5 4 4 3 3 ns Table 12: Typical Delay Estimated for Each Macrocell at T = 25 °C(Continued) ParameterDescriptionNote VDD = 1.0 V VDD = 1.2 V VDD = 1.5 V VDD = 1.65 V Unit Rising Falling Rising Falling Rising Falling Rising Falling |
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