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SLG47502V Datasheet(PDF) 44 Page - Renesas Technology Corp |
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SLG47502V Datasheet(HTML) 44 Page - Renesas Technology Corp |
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44 / 192 page  Datasheet 28-Feb-2023 CFR0011-120-00 Revision 2.3 44 of 194 © 2023 Renesas Electronics Corporation SLG47512/13 Low Voltage GreenPAK Programmable Mixed-Signal Matrix Preliminary Figure 17: DFF0 to DFF2 and Shift Register0 to Shift Register2 Operation with DFF Initial Value = 1 VDD Data Clk POR ShReg_Out[3:0] (Internal Signal) Initial Value 1001 (x9) 0010 0101 1010 0101 1011 0111 Inital Value is loaded from NVM to Shift Register Note1 : DFF Setting “Initial Value: 1” Note2 : Macrocell is configured as DFF Note3 : Macrocell is configured as 4-bits ShReg Q=ShReg_Out[0] (see note 2) Q=ShReg_Out[3] (see note 3) 4 Clk pulses |
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