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SLG47502V Datasheet(PDF) 92 Page - Renesas Technology Corp |
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SLG47502V Datasheet(HTML) 92 Page - Renesas Technology Corp |
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92 / 192 page ![]() Datasheet 28-Feb-2023 CFR0011-120-00 Revision 2.3 92 of 194 © 2023 Renesas Electronics Corporation SLG47512/13 Low Voltage GreenPAK Programmable Mixed-Signal Matrix Preliminary 9.1 ACMP0H BLOCK DIAGRAM Figure 73: ACMP0H Block Diagram Selectable Gain GPIOx: ACMP0H+ VDD to ACMP1H input MUX 111111 000000 100001 ... Internal Vref Registers [1493:1488] from Connection Matrix Output [93] Low Pass Filter* Ext. Vref0 Hysteresis Selection Registers [1495:1494] Pwr Up ACMP Ready LATCH 0 1 W/S Control Registers [953:952] to Connection Matrix Input [60] Registers [1499:1498] High Speed ACMP Note*: 2 nd order low pass filter typical bandwidth is 300 kHz 34 Vref GPIOx in analog IO mode; Registers [1500] 0 1 |
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