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SLG47502V Datasheet(PDF) 18 Page - Renesas Technology Corp |
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SLG47502V Datasheet(HTML) 18 Page - Renesas Technology Corp |
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18 / 192 page  Datasheet 28-Feb-2023 CFR0011-120-00 Revision 2.3 18 of 194 © 2023 Renesas Electronics Corporation SLG47512/13 Low Voltage GreenPAK Programmable Mixed-Signal Matrix Preliminary tVD_ACK Data Valid Acknowledge Time -- 900 ns tBUF Bus Free Time between Stop and Start 1300 -- ns tHD_STA Start Hold Time 600 -- ns tSU_STA Start Set-up Time 600 -- ns tHD_DAT Data Hold Time (Note 1) 200 -- ns tSU_DAT Data Set-up Time (Note 1) 223 -- ns tR Inputs Rise Time -- 300 ns tF Inputs Fall Time -- 300 ns tSU_STO Stop Set-up Time 600 -- ns tVD_DAT Data Valid Time -- 900 ns Note 1 Does not meet standard I2C specifications: tHD_DAT = 0 ns (min), tSU_DAT = 100 ns (min). Note 2 Timing diagram can be found in Figure 99. Table 10: I2C Pins Timing Characteristics for DILV Mode, T = -40 °C to +85 °C, Full VDD Range Unless Otherwise Noted Parameter Description Condition Speed Unit 400 kHz Min Max |
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