AD9461 datasheet(9/28 Pages) AD

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AD9461

Rev. 0 | Page 9 of 28

Pin No.

Mnemonic

Description

REFT

Differential Reference Output. Decoupled to ground with 0.1 μF capacitor and to REFB

(Pin 11) with 0.1 μF and 10 μF capacitors.

REFB

Differential Reference Output. Decoupled to ground with a 0.1 μF capacitor and to REFT

(Pin 10) with 0.1 μF and 10 μF capacitors.

12 to 17, 25 to 31, 35, 37

AVDD2

5.0 V Analog Supply (±5%).

VIN+

Analog Input—True.

VIN−

Analog Input—Complement.

CLK+

Clock Input—True.

CLK−

Clock Input—Complement.

47, 63, 75, 87

DRGND

Digital Output Ground.

48, 64, 76, 88

DRVDD

3.3 V Digital Output Supply (3.0 V to 3.6 V).

D0− (LSB)

D0 Complement Output Bit (LVDS Levels).

D0+

D0 True Output Bit.

D1−

D1 Complement Output Bit.

D1+

D1 True Output Bit.

D2−

D2 Complement Output Bit.

D2+

D2 True Output Bit.

D3−

D3 Complement Output Bit.

D3+

D3 True Output Bit.

D4−

D4 Complement Output Bit.

D4+

D4 True Output Bit.

D5−

D5 Complement Output Bit.

D5+

D5 True Output Bit.

D6−

D6 Complement Output Bit.

D6+

D6 True Output Bit.

D7−

D7 Complement Output Bit.

D7+

D7 True Output Bit.

DCO−

Data Clock Output—Complement.

DCO+

Data Clock Output—True.

D8−

D8 Complement Output Bit.

D8+

D8 True Output Bit.

D9−

D9 Complement Output Bit.

D9+

D9 True Output Bit.

D10−

D10 Complement Output Bit.

D10+

D10 True Output Bit.

D11−

D11 Complement Output Bit.

D11+

D11 True Output Bit.

D12−

D12 Complement Output Bit.

D12+

D12 True Output Bit.

D13−

D13 Complement Output Bit.

D13+

D13 True Output Bit.

D14−

D14 Complement Output Bit.

D14+

D14 True Output Bit.

D15−

D15 Complement Output Bit.

D15+ (MSB)

D15 True Output Bit.

OR−

Out-of-Range Complement Output Bit.

OR+

Out-of-Range True Output Bit.

100

SFDR

SFDR Control Pin. CMOS-compatible control pin for optimizing the configuration of the

AD9461 analog front end. Connecting SFDR to AGND optimizes SFDR performance for

applications with analog input frequencies <40 MHz or >215 MHz. For applications with

analog inputs from 40 MHz to 215 MHz, connect this pin to AVDD1 for optimum SFDR

performance; power dissipation from AVDD2 decreases by ~40 mW.

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