AD9461 datasheet(19/28 Pages) AD

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AD9461

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formance are nearly flat for a 30% to 70% duty cycle with the DCS

enabled. The DCS circuit locks to the rising edge of CLK+ and

optimizes timing internally. This allows for a wide range of input

duty cycles at the input without degrading performance. Jitter in

the rising edge of the input is still of paramount concern and is

not reduced by the internal stabilization circuit. The duty cycle

control loop does not function for clock rates of less than 30 MHz

nominally. The loop is associated with a time constant that

should be considered in applications where the clock rate can

change dynamically, requiring a wait time of 1.5 μs to 5 μs after a

dynamic clock frequency increase or decrease before the DCS

loop is relocked to the input signal. During the time that the

loop is not locked, the DCS loop is bypassed, and the internal

device timing is dependent on the duty cycle of the input clock

signal. In such an application, it can be appropriate to disable the

duty cycle stabilizer. In all other applications, enabling the DCS

circuit is recommended to maximize ac performance.

The DCS circuit is controlled by the DCS MODE pin; a CMOS

logic low (AGND) on DCS MODE enables the duty cycle stabilizer,

and logic high (AVDD1 = 3.3 V) disables the controller.

The AD9461 input sample clock signal must be a high quality,

extremely low phase noise source to prevent degradation of per-

formance. Maintaining 16-bit accuracy places a premium on the

encode clock phase noise. SNR performance can easily degrade

by 3 dB to 4 dB with 70 MHz analog input signals when using a

high jitter clock source. (See the AN-501 Application Note,

Aperture Uncertainty and ADC System Performance

for more

information.) For optimum performance, the AD9461 must be

clocked differentially. The sample clock inputs are internally

biased to ~1.5 V, and the input signal is usually ac-coupled into

the CLK+ and CLK− pins via a transformer or capacitors.

Figure 33 shows one preferred method for clocking the

AD9461. The clock source (low jitter) is converted from single-

ended to differential using an RF transformer. The back-to-back

Schottky diodes across the secondary of the transformer limit

clock excursions into the AD9461 to approximately 0.8 V p-p

differential. This helps prevent the large voltage swings of the

clock from feeding through to other portions of the AD9461 and

limits the noise presented to the sample clock inputs.

If a low jitter clock is available, it helps to band-pass filter the

clock reference before driving the ADC clock inputs. Another

option is to ac couple a differential ECL/PECL signal to the encode

input pins, as shown in Figure 34.

0.1µF

AD9461

CLK+

CLK–

HSMS2812

DIODES

CRYSTAL

SINE

SOURCE

ADT1–1WT

Figure 33. Crystal Clock Oscillator, Differential Encode

0.1µF

AD9461

ENCODE

0.1µF

ECL/

PECL

Figure 34. Differential ECL for Encode

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality

of the clock input. The degradation in SNR at a given input

frequency (fINPUT) and rms amplitude due only to aperture jitter

(tJ) can be calculated using the following equation:

SNR

= −20 log[2πfINPUT × tJ]

In the equation, the rms aperture jitter represents the root-mean-

square of all jitter sources including the clock input, analog input

signal, and ADC aperture jitter specification. IF undersampling

applications are particularly sensitive to jitter

The clock input should be treated as an analog signal in cases

where aperture jitter can affect the dynamic range of the AD9461.

Power supplies for clock drivers should be separated from the

ADC output driver supplies to avoid modulating the clock signal

with digital noise. Low jitter crystal-controlled oscillators make

the best clock sources. If the clock is generated from another type

of source (by gating, dividing, or another method), it should be

synchronized by the original clock during the last step.

POWER CONSIDERATIONS

Care should be taken when selecting a power source. The use of

linear dc supplies is highly recommended. Switching supplies

tend to have radiated components that can be received by the

AD9461. Each of the power supply pins should be decoupled as

closely to the package as possible using 0.1 μF chip capacitors.

The AD9461 has separate digital and analog power supply pins.

The analog supplies are denoted AVDD1 (3.3 V) and AVDD2

(5 V), and the digital supply pins are denoted DRVDD. Although

the AVDD1 and DRVDD supplies can be tied together, best per-

formance is achieved when the supplies are separate. This is

because the fast digital output swings can couple switching

current back into the analog supplies. Note that both AVDD1

and AVDD2 must be held within 5% of the specified voltage.

The DRVDD supply of the AD9461 is a dedicated supply for the

digital outputs in either LVDS or CMOS output mode. When in

LVDS mode, the DRVDD should be set to 3.3 V. In CMOS mode,

the DRVDD supply can be connected from 2.5 V to 3.6 V for

compatibility with the receiving logic.

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