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INA781 Datasheet(PDF) 31 Page - Texas Instruments |
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INA781 Datasheet(HTML) 31 Page - Texas Instruments |
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31 / 40 page ![]() 8.4.2 Layout Example 2 Address Lines A1, A0 via to connect directly to VS, GND, SDA, or SCL to set device address Device Bypass Capcitor I2C bus connections for clock and data (pullup resistors not shown) TI Device IS+ IS Place vias connecting to inner or bottom layers as close as possible to the device. The number of vias required depends on operational current and ambient conditions (1) All vias close to the pin pads should be tented. (2) All Vias are either 8 mil/18 mil or 15 mil/25 mil with a 5 mill annular ring. (3) The distance between the IS+ and IS- power pours is 8 mil. Figure 8-3. INA781 Layout Example www.ti.com INA781 SBOSAC0 – JULY 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: INA781 |
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