LTC4270 datasheet(16/34 Pages) AD

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Data Sheet

LTC9101-2A/LTC9102

PIN FUNCTIONS

analog.com

Rev. 0 | 16 of 34

Pin No.

Mnemonic

Description

LTC9101-2A

Pins 2, 1,

Respectively

CFG[1:0]

Device Configuration Inputs. Tie the

configuration pins high or low to

set number of ports and number of

connected LTC9102s. See Table 7 for

details.

Pins 7, 23,

Respectively

CAP[2:1]

Core Power Supply Bypass Capacitors.

Connect each pin to a 1μF capacitance

to DGND for the internal 1.2V regulator

bypass. Do not use other capacitor

values. Do not source or sink current

from this pin.

Pin 8

CPD

Clock Transceiver Positive Input Output

(Digital). Connect to CPA through a data

transformer.

Pin 9

CND

Clock Transceiver Negative Input

Output (Digital). Connect to CNA

through a data transformer.

Pin 10

DPD

Data Transceiver Positive Input Output

(Digital). Connect to DPA through a data

transformer.

Pin 11

DND

Data Transceiver Negative Input Output

(Digital). Connect to DNA through a

data transformer.

Pins 12, 19, 24

VDD

VDD IO Power Supply. Connect to

a 3.3V power supply relative to

DGND. Each VDD pin must be locally

bypassed with at least a 0.1µF

capacitor. A 10µF bulk capacitor must

be connected across VDD for increased

surge immunity.

Pin 14

RESET

Reset Input, Active Low. When RESET

is low, the LTC9101-2A/LTC9102 is

held inactive with all ports off and all

internal registers reset. When RESET is

pulled high, the LTC9101-2A/LTC9102

begins normal operation. RESET can

be connected to an external capacitor

or RC network to provide a power

turn-on delay. Internal filtering of

RESET prevents glitches less than 1µs

wide from resetting the LTC9101-2A/

LTC9102. Internally pulled up to VDD.

Pin 15

INT

Interrupt Output, Open Drain. INT

pulls low when any one of several

events occur in the LTC9101-2A. It

returns to a high impedance state when

bits 6 or 7 are set in the "Reset"

to generate an interrupt to the host

processor, eliminating the need for

continuous software polling. Individual

INT events can be disabled using

the "Int Mask" register. Refer to the

LTC9101-2A software interface data

Pin No.

Mnemonic

Description

sheet for more information. INT is only

updated between I2C transactions.

Pin 16

SDAOUT

Serial Data Output, Open Drain Data

Output for the I2C Serial Interface

Bus. The LTC9101-2A uses two pins

to implement the bidirectional SDA

function to simplify opto-isolation of

the I2C bus. To implement a standard

bidirectional SDA pin, tie SDAOUT

and SDAIN together. See Applications

Information for more information.

Pin 17

SDAIN

Serial Data Input. High impedance

data input for the I2C serial interface

bus. The LTC9101-2A uses two pins

to implement the bidirectional SDA

function to simplify opto-isolation of

the I2C bus. To implement a standard

bidirectional SDA pin, tie SDAOUT

and SDAIN together. See Applications

Information for more information.

Pin 18

SCL

Serial Clock Input. High impedance

clock input for the I2C serial interface

bus. The SCL pin should be connected

directly to the I2C SCL bus line. SCL

must be tied high if the I2C serial

interface bus is not used.

Pin 20

OSS

Maskable Shutdown Input, Active High.

Supports 1-bit shutdown priority. See

the Over Supply Shutdown (OSS))

section for details. Internally pulled

down to DGND.

Pins 21, 6, 5, 3,

Respectively

AD[4:1]

I2C Address Bits 4 to 1. Tie the address

pins high or low to set the base I2C

serial address. The base address is

(01A4A3A2A10b). Internally pulled up to

VDD. See Bus Addressing for details.

Pins 22, 25

DGND

Digital Ground. DGND should be

connected to the return from the VDD

supply.

LTC9102

Pin 1

CAP3

Analog Internal 3.3V Power Supply

Bypass Capacitor. Connect a 1μF

ceramic cap to VEE. A 3.3V power

supply may be connected to this pin

to improve power supply efficiency. The

EXT3 pin must be pulled to CAP3

to shut off the internal 3.3V regulator

if power is supplied externally. Do

not source or sink current from this

pin. Do not connect to CAP3 except

as explicitly instructed in the Analog

Devices documentation (for example,

strapping LTC9102 pins and terminating

the serial interface).

Pin 2

EXT3

External 3.3V Enable. Connect the

EXT3 pin to CAP3 to shut off the

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