LTC4270 datasheet(27/34 Pages) AD

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Data Sheet

LTC9101-2A/LTC9102

APPLICATIONS INFORMATION

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Rev. 0 | 27 of 34

High-Speed Data Interface

The communication between the LTC9101-2A and LTC9102s is

through a high-speed data interface over either a proprietary isola-

tion scheme or direct connection scheme. For proper operation,

strict layout guidelines must be met (see High-Speed Data Interface

Layout).

In the proprietary isolation scheme, the LTC9101-2A/LTC9102 chip-

set uses a single pair of transformers to isolate the LTC9101-2A

from one to four LTC9102s (see Figure 43). In this case, the SDAIN

and SDAOUT pins can be shorted to each other and tied directly

to the I2C/SMBus bus. The transformers should be 10Base-T or

10/100Base-T with a 1:1 turns ratio. Optimally, the selected trans-

formers do not have common-mode chokes. These transformers

typically provide 1500V of isolation between the LTC9101-2A and

the LTC9102s. Significant BOM cost reductions can be achieved

using the proprietary isolation scheme.

In the direct connection scheme, the LTC9101-2A/LTC9102 chip-

set relies on pre-existing system isolation. In this scheme, the

LTC9101-2A connects directly to one or more LTC9102s using a

proprietary communication protocol (see Figure 44).

External MOSFET

Careful selection of the power MOSFET is critical to system reliabil-

ity. Choosing a MOSFET requires extensive analysis and testing

of the MOSFET SOA curve against the various PSE current limit

conditions. Analog Devices recommends the PSMN075-100MSE

for PSEs configured to deliver up to 25.5W maximum pairset power.

These MOSFETs are selected for their proven reliability in PoE

applications. Contact Analog Devices applications support before

using a MOSFET other than this recommended part.

Sense Resistors

The LTC9101-2A/LTC9102 is designed for a low 0.1Ω current

sense resistance per port, laid out as shown in the Layout Require-

ments section, Figure 46. To meet the IHOLD, and ILIM accuracy

required by the IEEE specification, the sense resistors should have

±1% tolerance or better, and no more than ±200ppm/°C tempera-

ture coefficient.

Port Output Cap

Each port requires a 0.1μF cap across OUTn to AGND (see Figure

45) to keep the LTC9102 stable while in current limit during start-up

or overload. Common ceramic capacitors often have significant

voltage coefficients; this means the capacitance is reduced as the

applied voltage increases. To minimize this problem, X7R ceramic

capacitors rated for at least 100V are recommended and must be

located close to the LTC9102.

Surge Protection

Ethernet ports can be subject to significant cable surge events. To

keep PoE voltages below a safe level and protect the application

against damage, protection components, as shown in Figure 45,

are required at the main supply, at the LTC9102 supply pins, and at

each port.

Bulk transient voltage suppression (TVSBULK) and bulk capacitance

(CBULK) are required across the main PoE supply, and should be

sized to accommodate system level surge requirements.

Across each LTC9102 AGND pin and VEE pin is a SMAJ58A

58V TVS (D1) and a 1µF, 100V bypass capacitor (C1). These

components must be placed close to the LTC9102 pins.

Each port requires an S1B clamp diode from OUTn to supply

AGND. This diode steers harmful surges into the supply rails,

where they are absorbed by the surge suppressors and the VEE

bypass capacitance. The layout of these paths must be low impe-

dance.

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