LTC4270 datasheet(25/34 Pages) AD

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Data Sheet

LTC9101-2A/LTC9102

APPLICATIONS INFORMATION

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Rev. 0 | 25 of 34

The timing diagrams (Figure 30 through Figure 34) show typical

communication waveforms and their timing relationships. More

information about the SMBus data protocols can be found at

www.smbus.org.

Bus Addressing

The LTC9101-2A’s primary 7-bit serial bus address is

01A4A3A2A10b, with bits 4:1 set by AD[4:1] respectively. See Table

7 for device configuration options. Depending on device configura-

tion, up to 12 I2C addresses are populated from the I2C base

address upwards. All LTC9101-2As also respond to the broadcast

address 1111111b, allowing the host to write the same command

(typically configuration commands) to multiple LTC9101-2As in a

single transaction. If the LTC9101-2A is asserting INT, it also

responds to the alert response address (0001100b) per the SMBus

specification.

Each LTC9101-2A/LTC9102 is logically composed of multiple four

port groups, known as quads, each packed into a single I2C ad-

dress. See Device Configuration section for details. For example, if

CFG[1:0] is set to 00, an LTC9101-2A is configured as a 12-port de-

vice when attached to an LTC9102 (see Table 7). This configuration

requires consecutive I2C addresses, with quad offset 0 starting at

the I2C base address.

Interrupts and SMBAlert

Most port events can be configured to trigger an interrupt, asserting

INT and alerting the host to the event. This removes the need for

the host to poll the LTC9101-2A, minimizing serial bus traffic and

conserving host CPU cycles. Multiple LTC9101-2As can share a

common INT line, with the host using the SMBAlert protocol (ARA)

to determine which LTC9101-2A caused an interrupt.

For information on serial bus usage, and device configuration and

status, refer to the LTC9101-2A software interface data sheet,

which can be requested through the Analog Devices Software

Request Form.

ISOLATION REQUIREMENTS

IEEE 802.3 Ethernet specifications require that network segments

(including PoE circuitry) be electrically isolated from the chassis

ground of each network interface device. However, network seg-

ments are not required to be isolated from each other, provided

that the segments are connected to devices residing within a single

building on a single power distribution system.

If the PSE is part of a larger system, contains additional external

non-Ethernet ports, or must be referenced to protective ground for

some other reason, the PoE subsystem must be electrically isolated

from the rest of the system.

The LTC9101-2A/LTC9102 chipset simplifies PSE isolation by al-

lowing the LTC9101-2A chip to reside on the non-isolated side.

There it can receive power from the main logic supply and connect

directly to the I2C/SMBus bus. In this case, the SDAIN and SDA-

OUT pins can be tied together and act as a standard I2C/SMBus

SDA pin. Isolation between the LTC9101-2A and LTC9102 is im-

plemented using a proprietary transformer-based communication

protocol. The High-Speed Data Interface section of this data sheet

provides additional details.

For simple devices, such as unmanaged PoE switches, the isola-

tion requirement can be met using an isolated main power supply

for the entire device. This strategy can be used if the device has no

electrically conducting ports other than twisted-pair Ethernet. The

LTC9101-2A may directly connect to the LTC9102s in the above

circumstances, or if the system already provides isolation.

EXTERNAL COMPONENT SELECTION

Power Supplies

The LTC9101-2A/LTC9102 requires two supply voltages to operate.

VDD requires 3.3V (nominally) relative to DGND. VEE requires a

negative voltage of between –51V to –57V for Type 2 PSEs,

relative to AGND.

Digital Power Supply

VDD provides digital power for the LTC9101-2A processor. Place

a ceramic decoupling cap of at least 0.1μF from each VDD to

DGND, as close as practical to each LTC9101-2A. In addition, each

LTC9101-2A must include a bulk cap of 10µF for robust surge

immunity. A 1.2V core voltage supply is generated internally and

requires a 1µF ceramic decoupling cap between the CAP1 pin and

DGND, and between CAP2 and DGND.

In systems using Analog Devices' proprietary isolation, VDD should

be delivered by the host controller’s non-isolated 3.3V supply.

To maintain required isolation, LTC9102 AGND and LTC9101-2A

DGND must not be connected. If using the direct connection

scheme, the LTC9101-2A DGND must be connected to LTC9102

VEE.

Main PoE Power Supply

VEE is the main isolated PoE supply that provides power to the

PDs. Because it supplies a relatively large amount of power and

is subject to significant current transients, it requires more design

care than a simple logic supply. For minimum IR loss and best

system efficiency, set VEE near maximum amplitude (57V), leaving

enough margin to account for transient overshoot or undershoot,

temperature drift, and the line regulation specifications of the partic-

ular power supply used.

A bypass capacitor and a transient voltage suppressor (TVS) be-

tween each LTC9102 AGND and VEE are very important for reliable

operation. If a short circuit occurs at one of the output ports, it can

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