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TMS320DM6441 Datasheet(PDF) 64 Page - Texas Instruments |
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TMS320DM6441 Datasheet(HTML) 64 Page - Texas Instruments |
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64 / 229 page  www.ti.com 3.5 Configurations After Reset 3.5.1 Switched Central Resource (SCR) Bus Priorities TMS320DM6441 Digital Media System-on-Chip SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007 Table 3-11. GPIO and EMIFA Multiplexing (Part 3) Pin Mux Register AEAW[4:0] Bit Settings 10000 10001 10010 10011 10100 10101 10110 Others EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_BA[1] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[0] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[1] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[2] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[3] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[4] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[5] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[6] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[7] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[8] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[9] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[10] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[11] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[12] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[13] EM_A[14] EM_A[14] EM_A[14] EM_A[14] EM_A[14] EM_A[14] EM_A[14] EM_A[14] GPIO[16] EM_A[15] EM_A[15] EM_A[15] EM _A[15] EM_A[15] EM_A[15] EM_A[15] GPIO[15] GPIO[15] EM_A[16] EM_A[16] EM_A[16] EM_A[16] EM_A[16] EM_A[16] GPIO[14] GPIO[14] GPIO[14] EM_A[17] EM_A[17] EM_A[17] EM_A[17] EM_A[17] GPIO[13] GPIO[13] GPIO[13] GPIO[13] EM_A[18] EM_A[18] EM_A[18] EM_A[18] GPIO[12] GPIO[12] GPIO[12] GPIO[12] GPIO[12] EM_A[19] EM_A[19] EM_A[19] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] GPIO[11] EM_A[20] EM_A[20] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] GPIO[10] EM_A[21] The following sections give the details on configuring the device after reset. Prioritization within the switched central resource (SCR) is programmable for each master. The register bit fields and default priority levels for DM6441 bus masters are shown in Table 3-12. The priority levels should be tuned to obtain the best system performance for a particular application. Lower values indicate higher priority. For most masters, their priority values are programmed at the system level by configuring the MSTPRI0 and MSTPRI1 registers. Details on the MSTPRI0/1 registers are shown in Figure 3-5 and Figure 3-6. The C64x+, VPSS, and EDMA masters contain registers that control their own priority values. Device Configurations 64 Submit Documentation Feedback |
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