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TMS320DM6441 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320DM6441 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 229 page  www.ti.com 1 Digital Media System-on-Chip (DMSoC) 1.1 Features TMS320DM6441 Digital Media System-on-Chip SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007 (Flexible RAM/Cache Allocation) • High-Performance Digital Media SoC • ARM926EJ-S Core – C64x+™ DSP Clock Rate – Support for 32-Bit and 16-Bit (Thumb® • 405-MHz (Max) at 1.05 V or 513-MHz Mode) Instruction Sets (Max) at 1.2 V – DSP Instruction Extensions and Single – ARM926EJ-S™ Clock Rate Cycle MAC • 202.5-MHz (Max) at 1.05 V or 256-MHz – ARM® Jazelle® Technology (Max) at 1.2 V – Embedded ICE-RT™ Logic for Real-Time – Eight 32-Bit C64x+ Instructions/Cycle Debug – 4752 C64x+ MIPS • ARM9 Memory Architecture – Fully Software-Compatible With C64x / – 16K-Byte Instruction Cache ARM9™ – 8K-Byte Data Cache • Advanced Very-Long-Instruction-Word (VLIW) – 16K-Byte RAM TMS320C64x+™ DSP Core – 8K-Byte ROM – Eight Highly Independent Functional Units • Six ALUs (32-/40-Bit), Each Supports • Embedded Trace Buffer™ (ETB11™) With 4KB Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Memory for ARM9 Debug Arithmetic per Clock Cycle • Endianness: Little Endian for ARM and DSP • Two Multipliers Support Four 16 x 16-Bit • Video Processing Subsystem Multiplies (32-Bit Results) per Clock – Front End Provides: Cycle or Eight 8 x 8-Bit Multiplies (16-Bit • CCD and CMOS Imager Interface Results) per Clock Cycle • BT.601/BT.656 Digital YCbCr 4:2:2 – Load-Store Architecture With Non-Aligned (8-/16-Bit) Interface Support • Preview Engine for Real-Time Image – 64 32-Bit General-Purpose Registers Processing – Instruction Packing Reduces Code Size • Glueless Interface to Common Video – All Instructions Conditional Decoders – Additional C64x+™ Enhancements • Histogram Module • Protected Mode Operation • Auto-Exposure, Auto-White Balance, • Exceptions Support for Error Detection and Auto-Focus Module and Program Redirection • Resize Engine • Hardware Support for Modulo Loop • Resize Images From 1/4x to 4x Operation • Separate Horizontal/Vertical Control • C64x+ Instruction Set Features • Video Processing Subsystem (Continued) – Byte-Addressable (8-/16-/32-/64-Bit Data) – Back End Provides: – 8-Bit Overflow Protection • Hardware On-Screen Display (OSD) – Bit-Field Extract, Set, Clear • Four 54-MHz DACs for a Combination of – Normalization, Saturation, Bit-Counting • Composite NTSC/PAL Video – Compact 16-Bit Instructions • Luma/Chroma Separate Video – Additional Instructions to Support Complex (S-video) Multiplies • Component (YPbPr or RGB) Video • C64x+ L1/L2 Memory Architecture (Progressive) – 32K-Byte L1P Program RAM/Cache (Direct • Digital Output Mapped) • 8-/16-bit YUV or up to 24-Bit RGB – 80K-Byte L1D Data RAM/Cache (2-Way • HD Resolution Set-Associative) • Up to Two Video Windows – 64K-Byte L2 Unified Mapped RAM/Cache Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2006–2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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