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TMS320DM6441 Datasheet(PDF) 65 Page - Texas Instruments |
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TMS320DM6441 Datasheet(HTML) 65 Page - Texas Instruments |
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65 / 229 page  www.ti.com TMS320DM6441 Digital Media System-on-Chip SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007 Table 3-12. DM6441 Default Bus Master Priorities Priority Bit Field Bus Master Default Priority Level VPSSP VPSS 0 (VPSS PCR register) EDMATC0P EDMATC0 0 (EDMACC QUEPRI register) EDMATC1P EDMATC1 0 (EDMACC QUEPRI register) ARM_DMAP ARM (DMA) 1 (MSTPRI0 register) ARM_CFGP ARM (CFG) 1 (MSTPRI0 register) C64X+_DMAP C64X+ (DMA) 7 (C64x+ MDMAARBE.PRI register bit field) C64X+_CFGP C64X+ (CFG) 1 (MSTPRI0 register) EMACP EMAC 4 (MSTPRI1 register) USBP USB 4 (MSTPRI1 register) ATAP ATA/CF 4 (MSTPRI1 register) VLYNQP VLYNQ 4 (MSTPRI1 register) HPIP HPI 4 VICPP VICP 4 VICPP VICP 5 (MSTPRI0 Register) Figure 3-5. MSTPRI0 Register 31 19 18 16 RESERVED VICPP(1) R-0000 0000 0000 0 R/W-101 15 11 10 8 7 6 4 3 2 0 RESERVED C64X+_CFGP RSV ARM_CFGP RSV ARM_DMAP R-0000 0 R/W-001 R-0 R/W-001 R-0 R/W-001 LEGEND: R = Read; W = Write; -n = value after reset (1) The VICPP bit field is configured by the third-party software. When modifying the MSTPRI0 register a read/modify/write must be performed to preserve the configuration set by the third-party software. Figure 3-6. MSTPRI1 Register 31 23 22 20 19 18 16 RESERVED RESERVED RSV VLYNQP R-0000 0000 0 R-100 R-0 R/W-100 15 14 12 11 10 8 7 6 4 3 2 0 RSV ATAP RSV USBP RSV RESERVED RSV EMACP R-0 R/W-100 R-0 R/W-100 R-0 R-100 R-0 R/W-100 LEGEND: R = Read; W = Write; -n = value after reset Submit Documentation Feedback Device Configurations 65 |
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