TMS320DM6441 datasheet(9/229 Pages) TI

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2.3.2

CP15

2.3.3

MMU

2.3.4

Caches and Write Buffer

TMS320DM6441

Digital Media System-on-Chip

SPRS359B – SEPTEMBER 2006 – REVISED JANUARY 2007

The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both

hardware and software debug. The ARM926EJ-S processor has a Harvard architecture and provides a

complete high performance subsystem, including:

• ARM926EJ -S integer core

• CP15 system control coprocessor

• Memory management unit (MMU)

• Separate instruction and data caches

• Write buffer

• Separate instruction and data tightly-coupled memories (TCMs) [internal RAM] interfaces

• Separate instruction and data AHB bus interfaces

• Embedded trace module and embedded trace buffer (ETM/ETB)

For more complete details on the ARM9, refer to the ARM926EJ-S Technical Reference Manual, available

at http://www.arm.com

The ARM926EJ-S system control coprocessor (CP15) is used to configure and control instruction and

data caches, tightly-coupled memories (TCMs), memory management unit (MMU), and other ARM

subsystem functions. The CP15 registers are programmed using the MRC and MCR ARM instructions,

when the ARM in a privileged mode such as supervisor or system mode.

The ARM926EJ-S MMU provides virtual memory features required by operating systems such as Linux™,

WindowCE®, Ultron®, ThreadX®, etc. A single set of two level page tables stored in main memory is used

to control the address translation, permission checks and memory region attributes for both data and

instruction accesses. The MMU uses a single unified translation lookaside buffer (TLB) to cache the

information held in the page tables. The MMU features are:

• Standard ARM architecture v4 and v5 MMU mapping sizes, domains and access protection scheme.

• Mapping sizes are:

–

1MB (sections)

–

64KB (large pages)

–

4KB (small pages)

–

1KB (tiny pages)

• Access permissions for large pages and small pages can be specified separately for each quarter of

the page (subpage permissions)

• Hardware page table walks

• Invalidate entire TLB, using CP15 register 8

• Invalidate TLB entry, selected by MVA, using CP15 register 8

• Lockdown of TLB entries, using CP15 register 10

The size of the instruction cache is 16KB, data cache is 8KB. Additionally, the caches have the following

features:

• Virtual index, virtual tag, and addressed using the modified virtual address (MVA)

• Four-way set associative, with a cache line length of eight words per line (32-bytes per line) and with

two dirty bits in the Dcache

• Dcache supports write-through and write-back (or copy back) cache operation, selected by memory

region using the C and B bits in the MMU translation tables.

• Critical-word first cache refilling

• Cache lockdown registers enable control over which cache ways are used for allocation on a line fill,

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